open the CPU Core1 negative sense and connect the RTN1
pin to a pull-up resistor.
The OFS/VFIXEN pin selects between the AMD defined
VFIX and SVI modes of operation and enables droop if
desired in SVI mode only. If OFS/VFIXEN is tied to VCC,
then SVI mode with no droop on the core output(s) is
selected. Connected to +3.3V, VFIX mode is active with no
droop on the core output(s). SVI mode with droop is enabled
when OFS/VFIXEN is tied to ground through a resistor sized
to set the core voltage positive offset. Further information is
provided in “Offset Resistor Selection” on page 17.
Serial VID Interface
The on-board Serial VID Interface (SVI) circuitry allows the
processor to directly control the Core and Northbridge voltage
reference levels within the ISL6265A. The SVC and SVD
states are decoded according to the PWROK and VFIXEN
inputs as described in the following sections. The ISL6265A
uses a digital-to-analog converter (DAC) to generate a
reference voltage based on the decoded SVI value. See
Figure 7 for a simple SVI interface timing diagram.
Pre-PWROK Metal VID
Assuming the OFS/VFIXEN pin is not tied to +3.3V during
controller configuration, typical motherboard start-up begins
with the controller decoding the SVC and SVD inputs to
determine the pre-PWROK metal VID setting (see Table 1).
Once the enable input (EN) exceeds the rising enable
threshold, the ISL6265A decodes and locks the decoded
value in an on-board hold register.
TABLE 1. PRE-PWROK METAL VID CODES
OUTPUT VOLTAGE (V)
The internal DAC circuitry begins to ramp Core and
Northbridge planes to the decoded pre-PWROK metal VID
output level. The digital soft-start circuitry ramps the internal
reference to the target gradually at a fixed rate of
approximately 2mV/µs. The controlled ramp of all output
VDD AND VDDNB
Interval 1 to 2: ISL6265A waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: EN locks core output configuration and pre-Metal VID code. All outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH indicating proper operation.
Interval 5 to 6: CPU detects VDDPWRGD high and drives PWROK high to allow ISL6265A to prepare for SVI code.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL6265A responds to VID-ON-THE-FLY code change.
Interval 8 to 9: PWROK is driven low and ISL6265A returns all outputs to pre-PWROK Metal VID level.
Interval 9 to 10: PWROK driven high once again by CPU and ISL6265A prepares for SVI code.
Interval 10 to 11: SVC and SVD data lines communicate new VID code.
Interval 11 to 12: ISL6265A drives outputs to new VID code level.
Post 12 : Enable falls and all internal drivers are tri-stated and PGOOD is driven low.
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID STARTUP
May 11, 2009