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6265AHRTZ Просмотр технического описания (PDF) - Intersil

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6265AHRTZ Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs Intersil
Intersil Intersil
6265AHRTZ Datasheet PDF : 23 Pages
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ISL6265A
an error amplifier that allows the controller to maintain a
0.5% voltage regulation accuracy throughout the VID range
from 0.75V to 1.55V. Voltage regulation accuracy is slightly
wider, ±5mV, over the VID range from 0.7375V to 0.5V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients result in
increased switching frequency, which gives the R3 regulator
a faster response than conventional fixed frequency PWM
controllers. In uniplane configurations, transient load current
is inherently shared between active phases due to the use of
a common hysteretic window voltage. Individual average
phase currents are monitored and controlled to equally
share current among the active phases.
Modulator
The ISL6265A modulator features Intersil’s R3 technology, a
hybrid of fixed frequency PWM control and variable frequency
hysteretic control (see Figure 5). Intersil’s R3 technology can
simultaneously affect the PWM switching frequency and PWM
duty cycle in response to input voltage and output load
transients. The R3 modulator synthesizes an AC signal VR,
which is an analog representation of the output inductor ripple
current. The duty-cycle of VR is the result of charge and
discharge current through a ripple capacitor CR. The current
through CR is provided by a transconductance amplifier gm
that measures the VIN and VO voltages. The positive slope of
VR can be written as determined by Equation 1:
VRPOS = (gm) ⋅ (VIN VOUT)
(EQ. 1)
The negative slope of VR can be written as determined by
Equation 2:
VRNEG = gm VOUT
(EQ. 2)
Where gm is the gain of the transconductance amplifier.
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor connected across the FSET and GND
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage
and VW is the higher threshold voltage. Figure 6 shows
PWM pulses being generated as VR traverses the VW and
VCOMP thresholds. The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of VR; it is inversely proportional to the voltage
between VW and VCOMP.
Initialization
Once sufficient bias is applied to the VCC pin, internal logic
checks the status of critical pins to determine the controller
operation profile prior to ENABLE. These pins include RTN1
which determines single vs two-phase operation and
OFS/VFIXEN for enabling/disabling the SVI interface and
core voltage droop. Depending on the configuration set by
these pins, the controller then checks the state of the SVC
and SVD pins to determine the soft-start target output
voltage level..
VIN
+
gmVIN
VO
+
gmVO
PWM FREQUENCY
CONTROL
+
V- W +
VR
+
-
CR TO VCOMP +
PWM
CONTROL
FSET
R
PWM Q
S
ISL6265A
FIGURE 5. MODULATOR CIRCUITRY
RIPPLE CAPACITOR VOLTAGE CR
WINDOW VOLTAGE VW
ERROR AMPLIFIER VOLTAGE VCOMP
PWM
FIGURE 6. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
Power-On Reset
The ISL6265A requires a +5V input supply tied to VCC and
PVCC to exceed a rising power-on reset (POR) threshold
before the controller has sufficient bias to guarantee proper
operation. Once this threshold is reached or exceeded, the
ISL6265A has enough bias to begin checking RTN1,
OFS/VFIXEN, ENABLE, and SVI inputs. Hysteresis between
the rising the falling thresholds assure the ISL6265A will not
inadvertently turn-off unless the bias voltage drops
substantially (see “Electrical Specifications” on page 8).
Core Configuration
The ISL6265A determines the core channel requirements of
the CPU based on the state of the RTN1 pin prior to ENABLE. If
RTN1 is low prior to ENABLE, both VDD0 and VDD1 core
planes are required. The core controllers operate as
independent single-phase regulators. RTN1 is connected to the
CPU Core1 negative sense point. For single core CPU designs
(uniplane), RTN1 is tied to a +1.8V or greater supply. Prior to
ENABLE, RTN1 is detected as HIGH and the ISL6265A drives
the core controllers as a two-phase multi-phase regulator. Dual
purpose motherboard designs should include resistor options to
11
FN6884.0
May 11, 2009
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