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6261AIRZ Просмотр технического описания (PDF) - Intersil

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6261AIRZ Single-Phase Core Regulator for IMVP-6® Mobile CPUs Intersil
Intersil Intersil
6261AIRZ Datasheet PDF : 34 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Functional Pin Description
ISL6261A
40 39 38 37 36 35 34 33 32 31
FDE 1
PMON 2
RBIAS 3
VR_TT# 4
NTC 5
SOFT 6
OCSET 7
VW 8
COMP 9
FB 10
GND PAD
(BOTTOM)
30 VID2
29 VID1
28 VID0
27 VCCP
26 LGATE
25 VSSP
24 PHASE
23 UGATE
22 BOOT
21 NC
11 12 13 14 15 16 17 18 19 20
FDE
Forced diode emulation enable signal. Logic high of FDE
with logic low of DPRSTP# forces the ISL6261A to operate
in diode emulation mode with an increased VW-COMP
voltage window.
PMON
Analog voltage output pin. The voltage potential on this pin
indicates the power delivered to the output.
RBIAS
A 147K resistor to VSS sets internal current reference.
VR_TT#
Thermal overload output indicator with open-drain output.
Over-temperature pull-down resistance is 10.
NTC
Thermistor input to VR_TT# circuit and a 60µA current
source is connected internally to this pin.
SOFT
A capacitor from this pin to GND pin sets the maximum slew
rate of the output voltage. The SOFT pin is the non-inverting
input of the error amplifier.
OCSET
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
7
VW
A resistor from this pin to COMP programs the switching
frequency (eg. 6.81k = 300kHz).
COMP
The output of the error amplifier.
FB
The inverting input of the error amplifier.
VDIFF
The output of the differential amplifier.
VSEN
Remote core voltage sense input.
RTN
Remote core voltage sense return.
DROOP
The output of the droop amplifier. DROOP-VO voltage is the
droop voltage.
DFB
The inverting input of the droop amplifier.
VO
An input to the IC that reports the local output voltage.
FN6354.3
November 5, 2009
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