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62382CHRTZ Просмотр технического описания (PDF) - Intersil

Номер в каталогеКомпоненты Описаниепроизводитель
62382CHRTZ High-Efficiency, Quad or Triple-Output System Power Supply Controller for Notebook Computers Intersil
Intersil Intersil
62382CHRTZ Datasheet PDF : 23 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C
Pin Descriptions
PIN NUMBER
28 LD
1
2
3
4
5
-
6
7
8
9
10
11
12
13
14
15
16
-
-
-
17
18
19
20
21
22
23
24
25
26
27
32 LD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NAME
FUNCTION
PGOOD2 SMPS2 open-drain power-good status output. Connect to LDO5 through a 100kresistor. Output will be high when
the SMPS2 output is within the regulation window with no faults detected.
FSET2 Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. A small
ceramic capacitor such as 10nF is necessary to parallel with this resistor to smooth the voltage.
FCCM Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full
discontinuous conduction mode (DCM). Float this pin for ultrasonic DCM operation.
VCC2 SMPS2 analog power supply input for reference voltages and currents. Connect to VCC1 with a 10resistor.
Bypass to ground with a 1µF ceramic capacitor near the IC.
VCC1 SMPS1 analog power supply input for reference voltages and currents. It is internally connected to the LDO5
output. Bypass to ground with a 1µF ceramic capacitor near the IC.
LDO3EN Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input.
FSET1 Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. A small
ceramic capacitor such as 10nF is necessary to parallel with this resistor to smooth the voltage.
PGOOD1 SMPS1 open-drain power-good status output. Connect to LDO5 through a 100kresistor. Output will be high when
the SMPS1 output is within the regulation window with no faults detected.
FB1 SMPS1 feedback input used for output voltage programming and regulation.
VOUT1 SMPS1 output voltage sense input. Used for soft-discharge.
ISEN1 SMPS1 current sense input. Used for overcurrent protection and R3 regulation.
OCSET1 Input from current-sensing network used to program the overcurrent shutdown threshold for SMPS1.
EN1 Logic input to enable and disable SMPS1. A logic high will enable SMPS1 immediately. A logic low will disable
SMPS1. Floating this input will delay SMPS1 start-up until after SMPS2 achieves regulation.
PHASE1 SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching
NMOS source, the synchronous NMOS drain, and the output inductor for SMPS1.
UGATE1 High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET.
BOOT1 SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to PHASE1 with a 0.22µF ceramic capacitor.
LGATE1 Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.
LDO3FB LDO3 linear regulator feedback input used for output voltage programming and regulation.
LDO3 LDO3 linear regulator output, providing up to 100mA. Bypass to ground with a 4.7µF ceramic capacitor.
LDO3IN Power input for LDO3. Must be connected to a voltage greater than the LDO3 set point plus the dropout voltage.
VIN Feed-forward input for line voltage transient compensation. Connect to the power train input voltage.
LDO5 5V linear regulator output, providing up to 100mA before switchover to SMPS2. Bypass to ground with a 4.7µF
ceramic capacitor.
PGND Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents.
LGATE2 Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET.
BOOT2 SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to PHASE2 with a 0.22µF ceramic capacitor.
UGATE2 High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET.
PHASE2 SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching
NMOS source, the synchronous NMOS drain, and the output inductor for SMPS2.
EN2 Logic input to enable and disable SMPS2. A logic high will enable SMPS2 immediately. A logic low will disable
SMPS2. Floating this input will delay SMPS2 start-up until after SMPS1 achieves regulation.
OCSET2 Input from current-sensing network used to program the over-current shutdown threshold for SMPS2.
ISEN2 SMPS2 current sense input. Used for overcurrent protection and R3 regulation.
VOUT2 SMPS2 output voltage sense input. Used for soft-discharge and switchover to LDO5 output.
8
FN6665.5
May 13, 2011
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