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62382HRTZ Просмотр технического описания (PDF) - Intersil

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62382HRTZ High-Efficiency, Quad or Triple-Output System Power Supply Controller for Notebook Computers Intersil
Intersil Intersil
62382HRTZ Datasheet PDF : 23 Pages
First Prev 21 22 23
ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C
CSEN to the output side pad of the inductor. The ISEN
resistor should also be connected to the output pad of the
inductor with a separate trace. Connect the OCSET pin to
the common node of node of ROCSET and CSEN.
For resistive current sensing, connect ROCSET from the
OCSET pin to the inductor side of the resistor pad. The ISEN
resistor should be connected to the VOUT side of the resistor
pad.
In both current-sense configurations, the resistor and
capacitor sensing elements, with the exclusion of the current
sense power resistor, should be placed near the
corresponding IC pin. The trace connections to the inductor
or sensing resistor should be treated as Kelvin connections.
FB (Pins 9 and 32), and VOUT (Pins 10 and 31)
The VOUT pin is used to generate the R3 synthetic ramp
voltage and for soft-discharge of the output voltage during
shutdown events. This signal should be routed as close to
the regulation point as possible. The input impedance of the
FB pin is high, so place the voltage programming and loop
compensation components close to the VOUT, FB, and GND
pins keeping the high impedance trace short.
FSET (Pins 2 and 7)
These pins require a quiet environment. The resistor RFSET
and capacitor CFSET should be placed directly adjacent to
these pins. Keep fast moving nodes away from these pins.
LGATE (Pins 17 and 24)
The signal going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route these traces in parallel with the trace from the
PGND pin. These two traces should be short, wide, and
away from other traces. There should be no other weak
signal traces in proximity with these traces on any layer.
BOOT (Pins 16 and 25), UGATE (Pins 15 and 26), and
PHASE (Pins 14 and 27)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UGATE and PHASE pins in parallel with
short and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
21
FN6665.5
May 13, 2011
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