62382CHRTZ View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
62382CHRTZ Datasheet PDF : 23 Pages
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ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C
Where:
- IVALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- tON is the time required to drive the device into
saturation
- tOFF is the time required to drive the device into cut-off
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as
Equation 27:
CBOOT = -----V----QB----O-g---O-----T-
(EQ. 27)
Where:
- Qg is the total gate charge required to turn on the
high-side MOSFET
- VBOOT, is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Qg, of 25nC at VGS = 5V, and a VBOOT of
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
VIASS TTOO
GGROOUUNNDD
PPLLAANNEE
ININDDUUCCTTOORR
HHIIGGHH--SSIIDDEE
MMOOSSFFEETTSS
GND
VOUT
OOUUTTPPUUTT
CCAAPPAACCITITOORSRS
SSCCHHOOTTTTKKYY
DDIIOODDEE
PHASE
NODE
LLOOWW--SSIDIDEE
MMOOSSFFEETTSS
INPPUUTT
VIN
CAPPAACCITITOORRSS
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
Because there are two SMPS outputs and only one PGND
pin, the power train of both channels should be laid out
symmetrically. The line of bilateral symmetry should be
drawn through pins 4 and 21 (pins 4 and 18 for ISL62383).
This layout approach ensures that the controller does not
favor one channel over another during critical switching
decisions. Figure 30 illustrates one example of how to
achieve proper bilateral symmetry.
Co
PIN 4 (VCC2)
PIN 21 (VIN)
L2
LINE OF SYMMETRY
ISL62381
AND ISL62382
L2 U2
Ci
Ci
L1 U1
PGND PLANE
PHASE PLANES
VOUT PLANES
VIN PLANE
L1
Co
FIGURE 30. SYMMETRIC LAYOUT GUIDE
Signal Ground and Power Ground
The bottom of these controllers TQFN package is the signal
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of these controllers to the island of
ground plane under the top layer using several vias for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground (PGND) plane.
The following pin descriptions use ISL62381 as an example.
PGND (Pin 23)
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN (Pin 21)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pins 4 and 5)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
LDO5 (Pin 22)
For best performance, place the decoupling capacitor very
close to the LDO5 and respective PGND pin, preferably on
the same side of the PCB as the ISL62381 IC.
EN (Pins 13 and 28) and PGOOD (Pins 1 and 8)
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET (Pins 12 and 29) and ISEN (Pins 11 and 30)
For DCR current sensing, current-sense network, consisting
of ROCSET and CSEN, needs to be connected to the
inductor pads for accurate measurement. Connect ROCSET
to the phase-node side pad of the inductor, and connect
20
FN6665.5
May 13, 2011
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