ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C
integrated inside the IC that connects across the FB pin and the
COMP signal. RTOP, RFB, CFB and CINT form the TypeII
compensator. The frequency domain transfer function is given
by Equation 15:
GCOMPs = sR1TO+PsCRINTTOP1++RsFBRFCBFCBFB
(EQ. 15)
CINT = 100pF
RFB
CFB
RTOP

VO
FB
COMP
EA
+
RBOTTOM
REF
ISL6238
FIGURE 27. COMPENSATION REFERENCE CIRCUIT
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R3 modulator used in
these controllers make the LC output filter resemble a first order
system in which the closed loop stability can be achieved with
the recommended TypeII compensation network. Intersil
provides a PCbased tool (example page is shown later) that
can be used to calculate compensation network component
values and help simulate the loop frequency response.
LDO5 Linear Regulator
In addition to the two SMPS outputs, these controllers also
provide two linear regulator outputs. LDO5 is fixed 5V LDO
output capable of sourcing 100mA continuous current.
When the output of SMPS2 is programmed to 5V, SMPS2 will
automatically take over the load of LDO5. This provides a
large power savings and boosts the efficiency. After
switchover to SMPS2, the LDO5 output current plus the
MOSFET drive current should not exceed 100mA in order to
guarantee the LDO5 output voltage in the range of 5V ±5%.
The total MOSFET drive current can be estimated by
Equation 16.
IDRIVE = Qg FSW
(EQ. 16)
where Qg is the total gate charge of all the power MOSFET
in two SMPS regulators. Then the LDO5 output load current
should be less than 100mAIDRIVE.
LDO3 Linear Regulator
ISL62381, ISL62381C, ISL62382 and ISL62382C include
LDO3 linear regulator whose output is adjustable from 1.2V to
5V through LDO3FB pin with a 1.2V reference voltage. It can
be independently enabled from both SMPS channels. Logic
high of LDO3EN will enable LDO3. LDO3 is capable of
sourcing 100mA continuous current and draws its power from
LDO3IN pin, which must be connected to a voltage greater than
the LDO3 output voltage plus the dropout voltage.
Currents in excess of the limit will cause the LDO3 voltage to
drop dramatically, limiting the power dissipation.
Thermal Monitor and Protection
LDO3 and LDO5 can dissipate nontrivial power inside these
controllers at high inputtooutput voltage ratios and full load
conditions. To protect the silicon, these controllers continually
monitor the die temperature. If the temperature exceeds
+150°C, all outputs will be turned off to sharply curtail power
dissipation. The outputs will remain off until the junction
temperature has fallen below +135°C.
General Application Design Guide
This design guide is intended to provide a highlevel
explanation of the steps necessary to design a singlephase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following section. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 17:
D = VVOIUNT
(EQ. 17)
The output inductor peaktopeak ripple current is written as
Equation 18:
IPP = VOUFTSW1L–D
(EQ. 18)
A typical stepdown DC/DC converter will have an IPP of
20% to 40% of the maximum DC output load current. The
value of IPP is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by Equation 19:
PCOPPER = ILOAD2 DCR
(EQ. 19)
Where ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be given
to the DCR selection. Another factor to consider when choosing
the inductor is its saturation characteristics at elevated
temperatures. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance CO
into which ripple current IPP can flow. Current IPP develops
out of the capacitor. These two voltages are written as
Equation 20:
VESR = IPP ESR
(EQ. 20)
and Equation 21:
18
FN6665.5
May 13, 2011