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62382HRTZ Просмотр технического описания (PDF) - Intersil

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62382HRTZ High-Efficiency, Quad or Triple-Output System Power Supply Controller for Notebook Computers Intersil
Intersil Intersil
62382HRTZ Datasheet PDF : 23 Pages
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ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C
Resistor ROCSET and capacitor CSEN form an RC network
to sense the inductor current. To sense the inductor current
correctly, not only in DC operation but also during dynamic
operation, the RC network time constant ROCSETCSEN
needs to match the inductor time constant L/DCR. The value
of CSEN is then written as Equation 10:
CSEN = -R----O-----C----S----E--L--T------D-----C-----R---
(EQ. 10)
For example, if L is 1.5µH, DCR is 4.5m, and ROCSET is
9kthe choice of CSEN = 1.5µH/(9kx 4.5m) = 0.037µF
Upon converter start-up, the CSEN capacitor bias is 0V. To
prevent false OCP during this time, a 10µA current source
flows out of the ISEN1 pin, generating a voltage drop on the
RO resistor, which should be chosen to have the same
resistance as ROCSET. When PGOOD pin goes high, the
ISEN1 pin current source will be removed.
When an OCP fault is declared, the PGOOD pin will
pull-down to 32and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage, or until VIN has decayed below
the falling POR threshold.
When using a discrete current sense resistor, inductor
time-constant matching is not required. Equation 7 remains
unchanged, but Equation 8 is modified in Equation 11:
VOCSET1VISEN1 = IL RSENSE 10A ROCSET
(EQ. 11)
Furthermore, Equation 9 is changed in Equation 12:
ROCSET = I--O-----C-----1--R-0----S----EA----N----S----E--
(EQ. 12)
Where RSENSE is the series power resistor for sensing
inductor current. For example, with an RSENSE = 1mand
an OCP target of 10A, ROCSET = 1k
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold for more
than 2µs. The FB pin voltage is 0.6V in normal operation.
The rising over voltage threshold is typically 116% of that
value, or 1.16*0.6V = 0.696V.
When an OVP fault is declared, the PGOOD pin will pull
down with 65and latch-off the converter. The OVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage, or until VIN has decayed below
the falling POR threshold.
For ISL62381, ISL62381C, ISL62383 and ISL62383C,
although the converter has latched-off in response to an
OVP fault, the LGATE gate-driver output will retain the ability
to toggle the low-side MOSFET on and off in response to the
output voltage transversing the OVP rising and falling
thresholds. The LGATE gate-driver will turn on the low-side
MOSFET to discharge the output voltage, thus protecting the
load from potentially damaging voltage levels. The LGATE
gate-driver will turn off the low-side MOSFET once the FB
pin voltage is lower than the falling overvoltage threshold for
more than 2µs. The falling overvoltage threshold is typically
106% of the reference voltage, or 1.06*0.6V = 0.636V. This
process repeats as long as the output voltage fault is
present, allowing the ISL62381, ISL62381C, ISL62383 and
ISL62383C to protect against persistent overvoltage
conditions.
For ISL62382 and ISL62382C, if OVP is detected, it simply tri-
states the PHASE node by turning UGATE and LGATE off.
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold for more than
2µs. The undervoltage threshold is typically 86% of the
reference voltage, or 0.86*0.6V = 0.516V. If a UVP fault is
declared, and the PGOOD pin will pull-down with 93and
latch-off the converter. The fault will remain latched until the
EN pin has been pulled below the falling enable threshold, or
if VIN has decayed below the falling POR threshold.
Programming the Output Voltage
When the converter is in regulation, there will be 0.6V
between the FB and GND pins. Connect a two-resistor
voltage divider across the OUT and GND pins with the
output node connected to the FB pin, as shown in Figure 27.
Scale the voltage-divider network such that the FB pin is
0.6V with respect to the GND pin when the converter is
regulating at the desired output voltage. The output voltage
can be programmed from 0.6V to 5.5V.
Programming the output voltage is written as Equation 13:
VOUT
=
VREF
1
+
R-----B--R--O---T-T--O--T---P-O----M---
(EQ. 13)
Where:
- VOUT is the desired output voltage of the converter
- The voltage to which the converter regulates the FB pin
is the VREF (0.6V)
- RTOP is the voltage-programming resistor that connects
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
- RBOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Choose RTOP first when compensating the control loop, and
then calculate RBOTTOM according to Equation 14:
RBOTTOM = V--V---O-R---U-E---T-F----–---R--V--T--R--O--E---P-F--
(EQ. 14)
Compensation Design
Figure 27 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. CINT is a 100pF capacitor
17
FN6665.5
May 13, 2011
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