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62382HRTZ Просмотр технического описания (PDF) - Intersil

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62382HRTZ High-Efficiency, Quad or Triple-Output System Power Supply Controller for Notebook Computers Intersil
Intersil Intersil
62382HRTZ Datasheet PDF : 23 Pages
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ISL62381, ISL62382, ISL62383, ISL62381C, ISL62382C, ISL62383C
Theory of Operation
Four Output Controller
The ISL62381, ISL62382, ISL62381C and ISL62382C
generate four regulated output voltages, including two PWM
controllers and two LDOs. The two PWM channels are
identical and almost entirely independent, with the exception
of sharing the GND pin. Unless otherwise stated, only one
individual channel is discussed, and the conclusion applies
to both channels.
PWM Modulator
The ISL62381, ISL62382, ISL62383, ISL62381C,
ISL62382C and ISL62383C modulator features Intersil’s R3
technology, a hybrid of fixed frequency PWM control and
variable frequency hysteretic control. Intersil’s R3 technology
can simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The R3 modulator synthesizes an AC signal VR,
which is an analog representation of the output inductor
ripple current. The duty-cycle of VR is the result of charge
and discharge current through a ripple capacitor CR. The
current through CR is provided by a transconductance
amplifier gm that measures the VIN and VO pin voltages.
The positive slope of VR can be written as Equation 1:
VRPOS = gm  VIN VOUT  CR
(EQ. 1)
The negative slope of VR can be written as Equation 2:
VRNEG = gm VOUT CR
(EQ. 2)
Where gm is the gain of the transconductance amplifier.
RIPPLE CAPACITOR VOLTAGE VR
WINDOW VOLTAGE VW
(WRT VCOMP)
ERROR AMPLIFIER
VOLTAGE VCOMP
PWM
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor connected across the FSET and GND
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage
and VCOMP + VW is the higher threshold voltage. Figure 23
shows PWM pulses being generated as VR traverses the
VCOMP and VCOMP + VW thresholds. The PWM switching
frequency is proportional to the slew rates of the positive and
negative slopes of VR; it is inversely proportional to the
voltage between VW and VCOMP. Equation 3 illustrates how
to calculate the window size based on output voltage and
frequency set resistor RW.
VW = gm VOUT  1 D  RW
(EQ. 3)
Programming the PWM Switching Frequency
These controllers do not use a clock signal to produce
PWMs. The PWM switching frequency FSW is programmed
by the resistor RW that is connected from the FSET pin to
the GND pin. The approximate PWM switching frequency
can be expressed as written in Equation 4:
FSW = -1---0--------C----1R---------R----W---
(EQ. 4)
For a desired FSW, the RW can be selected by Equation 5.
RW = -1---0--------C----R-1--------F---S----W----
(EQ. 5)
where CR = 17pF with ±20% error range. To smooth the
FSET pin voltage, a ceramic capacitor such as 10nF is
necessary to parallel with RW.
It is recommended that whenever the control loop
compensation network is modified, FSW should be checked
for the correct frequency and if necessary, adjust RW.
Power-On Reset
These controllers are disabled until the voltage at the VIN
pin has increased above the rising power-on reset (POR)
threshold voltage. The controller will be disabled when the
voltage at the VIN pin decreases below the falling POR
threshold.
In addition to VIN POR, the LDO5 pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut
down. This ensures that there is sufficient BOOT voltage to
enhance the upper MOSFET.
EN, Soft-Start and PGOOD
These controllers use a digital soft-start circuit to ramp the
output voltage of each SMPS to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the in-rush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pins are pulled
above their rising thresholds, the PGOOD Soft-Start Delay,
tSS, starts and the output voltage begins to rise. The FB pin
ramps to 0.6V in approximately 1.5ms and the PGOOD pin
goes to high impedance approximately 1.25ms after the FB
pin voltage reaches 0.6V.
14
FN6665.5
May 13, 2011
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