ISL29011IROZ-EVALZ View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
| ISL29011IROZ-EVALZ Datasheet PDF : 0 Pages | |||
ISL29011
Electrical Specifications VSUP(VDDD,VDDA) = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance, 16-bit ADC operation, unless otherwise specified.
(Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP MAX UNIT
VIRLED Voltage Head Room of IRDR Pin
tr
Rise Time for IRDR Source Current
tf
Fall Time for IRDR Source Current
fIRLED1 IR LED Modulation Frequency
fIRLED2 IR LED Modulation Frequency
ISUP (IRLED1) Supply Current of Proximity Sensing
ISUP (IRLED2) Supply Current of Proximity Sensing
Duty Cycle Duty Cycle of IR LED Modulation
RLOAD = 15Ω at IRDR pin, 20% to 80%
RLOAD = 15Ω at IRDR pin, 80% to 20%
Freq = 0 (Note 8)
Freq = 1 (Note 8)
IS<1:0> = 0, Freq = 0 (Note 8)
IS<1:0> = 0, Freq = 1 (Note 8)
VDD - 0.6
V
35
ns
10
ns
DC
kHz
360
kHz
101
mA
51
mA
50
%
PROX-IR
PROX
Differential ADC Output of IR and
Proximity Sensing With Object Far
Away to Provide No Reflection
IR and proximity sensing with Range 2 and Scheme 0;
15Ω @ IRDR pin, IS<1:0> = 0, Freq = 0; E = 210 lux,
Sunlight.
1.0
%
NOTES:
5. VSUP is the common voltage to VDDD and VDDA.
6. 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count against an illuminance level
of 300 lux fluorescent light.
7. 850nm infrared LED is used in production test. The 850nm LED irradiance is calibrated to produce the same DATA_IR count against an illuminance
level of 210 lux sunlight at sea level.
8. See “Register Set” on page 8.
I2C Electrical Specifications For SCL and SDA unless otherwise noted, VSUP(VDDD,VDDA) = 3V, TA = +25°C, REXT = 499kΩ 1% tolerance,
16-bit ADC operation (Note 9).
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP MAX UNIT
VI2C
fSCL
VIL
VIH
Vhys
Supply Voltage Range for I2C Interface
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
1.7
1.25
0.05VDD
3.63 V
400 kHz
0.55 V
V
V
VOL
Low-level output voltage (open-drain) at 4mA sink
current
Ii
Input Leakage for each SDA, SCL pin
0.4 V
-10
10 µA
tSP
Pulse width of spikes that must be suppressed by
the input filter
tAA
SCL Falling Edge to SDA Output Data Valid
50 ns
900 ns
Ci
Capacitance for each SDA and SCL pin
10 pF
tHD:STA Hold Time (Repeated) START Condition
After this period, the first clock pulse is
600
ns
generated.
tLOW
LOW Period of the SCL clock
Measured at the 30% of VDD crossing.
1300
ns
tHIGH
HIGH period of the SCL Clock
600
ns
tSU:STA Set-up Time for a Repeated START Condition
600
ns
tHD:DAT
tSU:DAT
tR
tF
Data Hold Time
Data Set-up Time
Rise Time of both SDA and SCL Signals
Fall Time of both SDA and SCL Signals
30
ns
100
ns
20 + 0.1xCb
ns
20 + 0.1xCb
ns
5
FN6467.3
February 4, 2010
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