IS25LQ032C View Datasheet(PDF) - Integrated Silicon Solution
Part Name
Description
Manufacturer
IS25LQ032C
Integrated Silicon Solution
IS25LQ032C Datasheet PDF : 54 Pages
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IS25LQ032C
DEVICE OPERATION (CONTINUED)
FRDIO COMMAND (FAST READ DUAL I/O) OPERATION
The FRDIO instruction is similar to the FRDO
instruction, but allows the address bits to be input two
bits at a time. This may allow for code to be executed
directly from the SPI in some applications.
The FRDIO instruction code is followed by three
address bytes (A23 – A0) and a mode byte,
transmitted via the IO0 and IO1 lines, with each pair of
bits latched-in during the rising edge of SCK. The
address MSb is input on IO1, the next bit on IO0, and
continues to shift in alternating on the two lines. The
mode byte contains the value Ax, where x is a “don’t
care” value. Then the first data byte addressed is
shifted out on the IO1 and IO0 lines, with each pair of
bits shifted out at a maximum frequency fCT, during the
falling edge of SCK. The MSb is output on IO1, while
simultaneously the second bit is output on IO0. Figure
15 illustrates the timing sequence.
The first byte addressed can be at any memory
location. The address is automatically incremented
after each byte of data is shifted out. When the highest
address is reached, the address counter will roll over to
the 000000h address, allowing the entire memory to be
read with a single FRDIO instruction. FRDIO
instruction is terminated by driving CE# high (VIH).
The device expects the next operation will be another
FRDIO. It remains in this mode until it receives a
Mode Reset (FFh) command. In subsequent FRDIO
execution, the command code is not input, saving
timing cycles as described in Figure 16. If a FRDIO
instruction is issued while an Erase, Program or Write
cycle is in process (BUSY=1) the instruction is ignored
and will not have any effects on the current cycle
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
21
08/20/2012
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