Fig. 9 - Maximum Safe Operating Area
IRL520, SiHL520
Vishay Siliconix
VDS
VGS
RG
RD
D.U.T.
5V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
+- VDD
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on) tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
Vary tp to obtain
required IAS
RG
5V
tp
L
D.U.T.
IAS
0.01 Ω
+
- V DD
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91298
S-Pending-Rev. A, 21-Jul-08
VDS
VDS
tp
VDD
IAS
Fig. 12b - Unclamped Inductive Waveforms
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