ST95040B1 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST95040B1

4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe

STMicroelectronics 

ST95040, ST95020, ST95010

Hold (HOLD). The HOLD pin is used to pause

serial communications with the Memory without

resetting the serial sequence. To take the Hold

condition into account, the product must be se-

lected (S = 0). Then the Hold state is validated by

a high to low transition on HOLD when C is low. To

resume the communications, HOLDis brought high

while C is low. During the Hold condition D, Q, and

C are at a high impedance state.

When the Memory is under the Hold condition, it is

possible to deselect the device. However, the serial

communications will remain paused after a rese-

lect, and the chip will be reset.

The Memory can be driven by a microcontroller with

its SPI peripheral running in either of the two fol-

lowing modes: (CPOL, CPHA) = (’0’, ’0’) or (CPOL,

CPHA) = (’1’, ’1’).

For these two modes, input data is latched in by the

low to high transition of clock C, and output data is

available from the high to low transition of Clock

(C).

The difference between (CPOL, CPHA) = (0, 0) and

(CPOL, CPHA) = (1, 1) is the stand-by polarity: C

remains at ’0’ for (CPOL, CPHA) = (0, 0) and C

remains at ’1’ for (CPOL, CPHA) = (1, 1) when there

is no data transfer.

OPERATIONS

All instructions, addresses and data are shifted in

and out of the chip MSB first. Data input (D) is

sampled on the first rising edge of clock (C) after

the chip select (S) goes low. Prior to any operation,

a one-byte instruction code must be entered in the

chip. This code is entered via the data input (D),

and latched on the rising edge of the clock input

(C). To enter an instruction code, the product must

have been previously selected (S = low). Table 3

shows the instruction set and format for device

operation. If an invalid instruction is sent (one not

contained in Table 3), the chip is automatically

deselected. For operations that read or write data

in the memory array, bit 3 of the instruction is the

MSB of the address, otherwise, it is a don’t care.

Write Enable (WREN) and Write Disable (WRDI)

The Memory contains a write enable latch. This

latch must be set prior to every WRITE or WRSR

operation. The WREN instruction will set the latch

and the WRDI instruction will reset the latch. The

latch is reset under the following conditions:

– W pin is low

– Power on

– WRDI instruction executed

– WRSR instruction executed

– WRITE instruction executed

As soon as the WREN or WRDI instruction is

received by the memory, the circuit executes the

instruction and enters a wait mode until it is dese-

lected.

Read Status Register (RDSR)

The RDSR instruction provides access to the status

register. The status register may be read at any

time, even during a write to the memory operation.

If a Read Status register reaches the 8th bit of the

Status register, an additional 9th clock pulse will

wrap around to read the 1st bit of the Status Reg -

ister

The status register format is as follows:

b7

b0

1

1

1

1 BP1 BP0 WEL WIP

BP1, BP0: Read and write bits

WEL, WIP: Read only bits.

b7 to b4: Read only bits.

Table 3. Instruction Set

Instruction

WREN

WRDI

RDSR

WRSR

READ

WRITE

Description

Set Write Enable Latch

Reset Write Enable Latch

Read Status Register

Write Status Register

Read Data from Memory Array

Write Data to Memory Array

Notes: A8 = 1, Upper page selected on ST95040.

A8 = 0, Lower page selected on ST95040.

Instruction Format

0000 0110

0000 0100

0000 0101

0000 0001

0000 A8011

0000 A8010

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