ST95010B6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST95010B6

4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe

STMicroelectronics 

Figure 3. Data and Clock Timing

CPOL CPHA

0

0

C

1

1

C

D or Q

MSB

Figure 4. Microcontroller and SPI Interface Set-up

MICROCONTROLLER

(ST6, ST7, ST9, ST10, OTHERS)

SPI Interface with

(CPOL, CPHA) =

('0', '0') or ('1', '1')

SCK

SDI

SDO

ST95040, ST95020, ST95010

LSB

AI01438

C ST95xx0

Q

D

AI01439B

Serial Clock (C). The serial clock provides the

timing of the serial interface. Instructions, ad-

dresses, or data present at the input pin are latched

on the rising edge of the clock input, while data on

the Q pin changes after the falling edge of the clock

input.

Chip Select (S). When S is high, the Memory is

deselected and the Q output pin is at high imped-

ance and, unless an internal write operation is

underway the Memory will be in the standby power

mode. S low enables the Memory, placing it in the

active power mode. It should be noted that after

power-on, a high to low transition on S is required

prior to the start of any operation.

Write Protect (W). This pin is for hardware write

protection. When W is low, writes to the Memory

are disabled but any other operations stay enabled.

When W is high, all writes operations are available.

W going low at any time before the last bit D0 of

the data stream will reset the write enable latch and

prevent programming. No action on W or on the

write enable latch can interrupt a write cycle which

has commenced.

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