IP101A View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

IP101A

Single port 10/100 Fast Ethernet Transceiver

Unspecified 

Pin Descriptions (continued)

IP101A LF

Data Sheet

Pin no.

Label

Type

Description

LED and PHY Address Configuration

These five pins are latched into the IP101A LF during reset to configure PHY address [4:0] used for MII

management register interface. And then, in normal operation after initial reset, they are used as driving

pins for status indication LED. The driving polarity, active low or active high, is determined by each

latched status of the PHY address [4:0] during reset. If latched status is high then it will be active low,

and if latched status is Low then it will be active high. Moreover, IP101A LF provides 2 LED operation

modes. If 2nd LED mode is selected by pulling up pin CRS, only 4 LEDs are needed for status

indication. Default is first LED mode.

LED0

LED1

LED2

LED3

LED4

LED mode 1

LINK

FULL DUPLEX

10BT /ACT(blinking)

100BT /ACT(blinking)

COL

LED mode 2

LINK /ACT(blinking)

FULL DUPLEX /COL(blinking)

10BT

100BT

Reserved

9

PHYAD0/

LED0

LI/O PHY Address [0]

Status:

Mode1: Active when linked.

Mode2: Active when linked and blinking when transmitting or

receiving data.

10 PHYAD1/

LED1

LI/O PHY Address [1]

Status:

Mode1: Active when in Full Duplex operation.

Mode2: Active when in Full Duplex operation and blinking when

collisions occur.

12 PHYAD2/

LED2

LI/O PHY Address [2]

Status:

Mode1: Active when linked in 10Base-T mode, and blinking

when transmitting or receiving data.

Mode2: Active when linked in 10Base-T mode.

13 PHYAD3/

LED3

LI/O PHY Address [3]

Status:

Mode1: Active when linked in 100Base-TX and blinking when

transmitting or receiving data.

Mode2: Active when linked in 100Base-TX mode.

15 PHYAD4/

LED4

LI/O PHY Address [4]

Status:

Mode1: Active when collisions occur.

Mode2: Reserved.

Copyright © 2004, IC Plus Corp.

10/36

Oct 22, 2007

IP101A LF-DS-R12

Share Link: