Electrical Characteristics
4.6.2 WDOG Reset Timing Parameters
Figure 13 shows the WDOG reset timing and Table 46 lists the timing parameters.
WATCHDOG_RST
(Input)
CC5
Figure 13. WATCHDOG_RST Timing Diagram
Table 46. WATCHDOG_RST Timing Parameters
ID
Parameter
Min
Max
Unit
CC5 Duration of WATCHDOG_RESET Assertion
1
—
TCKIL
NOTE
CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs.
4.6.3 AUDMUX Timing Parameters
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is hence governed by the SSI module.
4.6.4 Clock Amplifier Parameters (CKIH1, CKIH2)
The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave
or sinusoidal frequency source. No external series capacitors are required. Table 47 shows the CAMP
electrical parameters.
Table 47. CAMP Electrical Parameters (CKIH1, CKIH2)
Parameter
Input frequency
VIL (for square wave input)
VIH (for square wave input)
Sinusoidal input amplitude
Output duty cycle
Min
Typ
8.0
—
0
—
NVCC_PER3 - 0.25
—
0.4
—
45
50
Max
40.0
0.3
NVCC_PER3
VDD
55
Unit
MHz
V
V
Vp-p
%
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
48
Freescale Semiconductor