ILC7082-XX View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
ILC7082-XX Datasheet PDF : 16 Pages
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ILC7082
With reference to the block diagram in Figure 2, VOUT is fed
back to the error amplifier and is used as the supply voltage
for the internal components of the ILC7082. So any change
in VOUT will cause the error amplifier to try to compensate to
maintain VOUT at the set level and noise on VOUT will be
reflected into the supply of each internal component of the
ILC7082. The reference voltage, VREF, is influenced by the
CNOISE pin. Noise into this pin will add to the reference
voltage and be fed through the circuit. These factors will not
cause a problem if some simple steps are taken. Figure 5
shows where these added ESR resistances are present in the
typical LDO circuit.
VOUT IOUT
IC
COUT
RC 5 SOT-23-5
4
ILC7082
R*
CNOISE
VIN
1
23
R*
CIN
RF LDOTM
Regulator
ON
OFF
VOUT IOUT
I1
COUT
RPCB
RPCB
5 SOT-23-5 4
ILC7082
ESR
CNOISE
VIN
CIN
1
RPCB
23
RPCB
ON
OFF
Figure 6. Inherent PCB resistance
Figure 7 shows the effects of poor grounding and PCB lay-
out magnified by the ESR and PCB resistances and the accu-
mulation of current flows.
Note that particularly during high output load current, the
LDO regulator’s ground pin and the ground return for COUT
and CNOISE are not at the same potential as the system
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current loop
between COUT, CNOISE and the LDO regulator’s ground pin
will degrade performance of the LDO.
Figure 5. ESR Present in COUT and CNOISE
With this in mind, low ESR components will offer better per-
formance where the LDO may be subjected to large load
transients current. ESR is less of a problem with CIN as the
voltage fluctuations at the input will be filtered by the LDO.
However, being aware of these current flows, there is also
another potential source of induced voltage noise from the
resistance inherent in the PCB trace. Figure 6 shows where
the additive resistance of the PCB can manifest itself. Again
these resistances may be very small, but a summation of sev-
eral currents can develop detectable voltage ripple and will
be amplified by the LDO. In particular, the accumulation of
current flows in the ground plane can develop significant
voltages unless care is taken. With a degree of care, the
ILC7082 will yield outstanding performance.
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground
current and noise bypass current return of the LDO regulator.
Note that the key difference here is that COUT and CNOISE are
directly connected to the LDO regulator’s ground pin. The
LDO is then separately connected to the main ground plane
and returned to a single point system ground.
The layout of the LDO and its external components are also
based on some simple rules to minimize EMI and output
voltage ripple.
Note, the ground plane is the bottom layer of the PCB and
connects to top layer ground connections through vias.
Printed Circuit Board Layout Guidelines
As was mentioned in the previous section, to take full
advantage of any high performance LDO regulator requires
careful attention to grounding and printed circuit board
(PCB) layout.
8
REV. 1.6.2 11/17/04
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