IDT7205L120_96 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT7205L120_96

CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

Integrated Device Technology 

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Outputs:

FULL FLAG (FF) — The Full Flag (FF) will go LOW, inhibiting

further write operations, when the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go

LOW after 2048/4096/8192/16384 writes.

EMPTY FLAG (EF) — The Empty Flag (EF) will go LOW,

inhibiting further read operations, when the read pointer is equal

to the write pointer, indicating that the device is empty.

EXPANSION OUT/HALF-FULL FLAG (XO/HF) — This is a

dual-purpose output. In the single device mode, when Expan-

sion In (XI) is grounded, this output acts as an indication of a half-

full memory.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (HF) will be set to LOW

and will remain set until the difference between the write pointer

and read pointer is less than or equal to one half of the total

memory of the device. The Half-Full Flag (HF) is then reset by

the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is con-

nected to Expansion Out (XO) of the previous device. This

output acts as a signal to the next device in the Daisy Chain by

providing a pulse to the next device when the previous device

reaches the last location of memory. There will be an XO pulse

when the Write pointer reaches the last location of memory, and

an additional XO pulse when the Read pointer reaches the last

location of memory.

DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-

bit wide data. These outputs are in a high-impedance condition

whenever Read (R) is in a HIGH state.

RS

W

R

EF

, HF FF

NOTE:

1. W and R = VIH around the rising edge of RS.

t RSC

t RS

t RSS

t RSS

t EFL

t HFH, t FFH

Figure 2. Reset

t RSR

2661 drw 04

R

Q0–Q8

t RC

tA

t RPW

t RR

tA

t RLZ

t DV

DATAOUT VALID

t RHZ

DATAOUT VALID

W

D0–D8

t WC

t WPW

t WR

t DS

t DH

DATA IN VALID

DATA IN VALID

2661 drw 05

Figure 3. Asynchronous Write and Read Operation

5.04

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