IDT7203L12PB View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT7203L12PB

CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

Integrated Device Technology 

IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO

2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns

1.5V

1.5V

See Figure 1

2661 tbl 07

CAPACITANCE(1) (TA = +25°C, f = 1.0 MHz)

Symbol

Parameter

Condition

CIN(1)

Input Capacitance VIN = 0V

COUT(1,2) Output Capacitance VOUT = 0V

NOTES:

1. This parameter is sampled and not 100% tested.

2. With output deselected.

Max. Unit

10 pF

10 pF

2661 tbl 08

MILITARY AND COMMERCIAL TEMPERATURE RANGES

5V

D.U.T.

680Ω

1.1KΩ

30pF*

2661 drw 03

OR EQUIVALENT CIRCUIT

Figure 1. Output Load

*Includes jig and scope capacitances.

SIGNAL DESCRIPTIONS

Inputs:

DATA IN (D0–D8) — Data inputs for 9-bit wide data.

Controls:

RESET (RS) — Reset is accomplished whenever the Reset

(RS) input is taken to a LOW state. During reset, both internal

read and write pointers are set to the first location. A reset is

required after power-up before a write operation can take place.

Both the Read Enable (R) and Write Enable (W) inputs must

be in the HIGH state during the window shown in Figure 2

(i.e. tRSS before the rising edge of RS) and should not

change until tRSR after the rising edge of RS.

WRITE ENABLE (W) — A write cycle is initiated on the falling

edge of this input if the Full Flag (FF) is not set. Data set-up and

hold times must be adhered-to, with respect to the rising edge

of the Write Enable (W). Data is stored in the RAM array

sequentially and independently of any on-going read operation.

After half of the memory is filled, and at the falling edge of the

next write operation, the Half-Full Flag (HF) will be set to LOW,

and will remain set until the difference between the write pointer

and read pointer is less-than or equal to one-half of the total

memory of the device. The Half-Full Flag (HF) is reset by the

rising edge of the read operation.

To prevent data overflow, the Full Flag (FF) will go LOW on

the falling edge of the last write signal, which inhibits further write

operations. Upon the completion of a valid read operation, the

Full Flag (FF) will go HIGH after tRFF, allowing a new valid write

to begin. When the FIFO is full, the internal write pointer is

blocked from W, so external changes in W will not affect the FIFO

when it is full.

READ ENABLE (R) — A read cycle is initiated on the falling

edge of the Read Enable (R), provided the Empty Flag (EF) is not

set. The data is accessed on a First-In/First-Out basis, inde-

pendent of any ongoing write operations. After Read Enable (R)

goes HIGH, the Data Outputs (Q0 through Q8) will return to a

high-impedance condition until the next Read operation. When

all the data has been read from the FIFO, the Empty Flag (EF)

will go LOW, allowing the “final” read cycle but inhibiting further

read operations, with the data outputs remaining in a high-

impedance state. Once a valid write operation has been accom-

plished, the Empty Flag (EF) will go HIGH after tWEF and a valid

Read can then begin. When the FIFO is empty, the internal read

pointer is blocked from R so external changes will not affect the

FIFO when it is empty.

FIRST LOAD/RETRANSMIT (FL/RT) — This is a dual-

purpose input. In the Depth Expansion Mode, this pin is

grounded to indicate that it is the first device loaded (see

Operating Modes). The Single Device Mode is initiated by

grounding the Expansion In (XI).

The IDT7203/7204/7205/7206 can be made to retransmit

data when the Retransmit Enable Control (RT) input is pulsed

LOW. A retransmit operation will set the internal read pointer to

the first location and will not affect the write pointer. The status

of the Flags will change depending on the relative locations of

the read and write pointers. Read Enable (R) and Write Enable

(W) must be in the HIGH state during retransmit. This feature is

useful when less than 2048/4096/8192/16384 writes are per-

formed between resets. The retransmit feature is not compat-

ible with the Depth Expansion Mode.

EXPANSION IN (XI) — This input is a dual-purpose pin.

Expansion In (XI) is grounded to indicate an operation in the

single device mode. Expansion In (XI) is connected to Expan-

sion Out (XO) of the previous device in the Depth Expansion or

Daisy-Chain Mode.

5.04

6

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