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IDT7203S65 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT7203S65 IDT
Integrated Device Technology IDT
DescriptionCMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
IDT7203S65 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) (Continued)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Military
Com'l & Mil.
Military(2)
7203S/L40
7204S/L40
7203S/L50
7204S/L50
7205L50
7206L50
7203S/L65 7203S/L80 7203S/L120
7204S/L65 7204S/L80 7204S/L120
Symbol
Parameters
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS
Shift Frequency
20 —
15 — 12.5 — 10 —
7 MHz
tRC
Read Cycle Time
50
— 65
— 80 — 100 — 140 —
ns
tA
Access Time
40 —
50 — 65 — 80 — 120 ns
tRR
Read Recovery Time
10
— 15
— 15 — 20 — 20 —
ns
tRPW
Read Pulse Width(3)
40
— 50
— 65 — 80 — 120 —
ns
tRLZ
Read LOW to Data Bus LOW(4)
5
— 10
— 10 — 10 — 10 —
ns
tWLZ
Write HIGH to Data Bus Low-Z(4, 5) 10
— 15
— 15 — 20 — 20 —
ns
tDV
Data Valid from Read HIGH
5
—5
—5
—5
—5
ns
tRHZ
Read HIGH to Data Bus High-Z(4)
25 —
30 — 30 — 30 — 35
ns
tWC
Write Cycle Time
50
— 65
— 80 — 100 — 140 —
ns
tWPW
Write Pulse Width(3)
40
— 50
— 65 — 80 — 120 —
ns
tWR
Write Recovery Time
10
— 15
— 15 — 20 — 20 —
ns
tDS
Data Set-up Time
20
— 30
— 30 — 40 — 40 —
ns
tDH
Data Hold Time
0
—5
— 10 — 10 — 10 —
ns
tRSC
Reset Cycle Time
50
— 65
— 80 — 100 — 140 —
ns
tRS
Reset Pulse Width(3)
40
— 50
— 65 — 80 — 120 —
ns
tRSS
Reset Set-up Time(4)
40
— 50
— 65 — 80 — 120 —
ns
tRSR
Reset Recovery Time
10
— 15
— 15 — 20 — 20 —
ns
tRTC
Retransmit Cycle Time
50
— 65
— 80 — 100 — 140 —
ns
tRT
Retransmit Pulse Width(3)
40
— 50
— 65 — 80 — 120 —
ns
tRTS
Retransmit Set-up Time(4)
40
— 50
— 65 — 80 — 120 —
ns
tRSR
Retransmit Recovery Time
10
— 15
— 15 — 20 — 20 —
ns
tEFL
Reset to EF LOW
50 —
65 — 80 — 100 — 140 ns
tHFH, tFFH Reset to HF and FF HIGH
50 —
65 — 80 — 100 — 140 ns
tRTF
Retransmit LOW to Flags Valid
50 —
65 — 80 — 100 — 140 ns
tREF
Read LOW to EF Flag LOW
35 —
45 — 60 — 60 — 60
ns
tRFF
Read HIGH to FF HIGH
35 —
45 — 60 — 60 — 60
ns
tRPE
Read Pulse Width after EF HIGH
40
— 50
— 65 — 80 — 120 —
ns
tWEF
Write HIGH to EF HIGH
35 —
45 — 60 — 60 — 60
ns
tWFF
Write LOW to FF LOW
35 —
45 — 60 — 60 — 60
ns
tWHF
Write LOW to HF LOW
50 —
65 — 80 — 100 — 140 ns
tRHF
Read HIGH to HF HIGH
50 —
65 — 80 — 100 — 140 ns
tWPF
Write Pulse Width after FF HIGH
40
— 50
— 65 — 80 — 120 —
ns
tXOL
Read/Write LOW to XO LOW
40 —
50 — 65 — 80 — 120 ns
tXOH
Read/Write HIGH to XO HIGH
40 —
50 — 65 — 80 — 120 ns
tXI
XI Pulse Width(3)
40
— 50
— 65 — 80 — 120 —
ns
tXIR
XI Recovery Time
10
— 10
— 10 — 10 — 10 —
ns
tXIS
XI Set-up Time
15
— 15
— 15 — 15 — 15 —
ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
3. Pulse widths less than minimum are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
2661 tbl 06
5.04
5
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