IDT7282LA25SOGB8 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

Manufacturer

IDT7282LA25SOGB8

CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9

Integrated Device Technology 

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS(1) (Continued)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Military

IDT7200L30

IDT7201LA30

IDT7202LA30

Commercial

IDT7200L35

IDT7201LA35

IDT7202LA35

Com'l & Mil.(2)

IDT7200L50

IDT7201LA50

IDT7202LA50

Military(2)

IDT7201LA80

Symbol

Parameter

Min. Max.

Min.

Max. Min.

Max. Min.

Max. Unit

tS

Shift Frequency

—

25

—

22.2

—

15

—

10 MHz

tRC

Read Cycle Time

40

—

45

—

65

—

100

—

ns

tA

Access Time

—

30

—

35

—

50

—

80

ns

tRR

Read Recovery Time

10

—

10

—

15

—

20

—

ns

tRPW

Read Pulse Width(3)

30

—

35

—

50

—

80

—

ns

tRLZ

Read Pulse Low to Data Bus at Low Z(4)

3

—

3

—

3

—

3

—

ns

tWLZ

Write Pulse High to Data Bus at Low Z(4, 5)

5

—

5

—

5

—

5

—

ns

tDV

Data Valid from Read Pulse High

5

—

5

—

5

—

5

—

ns

tRHZ

Read Pulse High to Data Bus at High Z(4)

—

20

—

20

—

30

—

30

ns

tWC

Write Cycle Time

40

—

45

—

65

—

100

—

ns

tWPW

Write Pulse Width(3)

30

—

35

—

50

—

80

—

ns

tWR

Write Recovery Time

10

—

10

—

15

—

20

—

ns

tDS

Data Set-up Time

18

—

18

—

30

—

40

—

ns

tDH

Data Hold Time

0

—

0

—

5

—

10

—

ns

tRSC

Reset Cycle Time

40

—

45

—

65

—

100

—

ns

tRS

Reset Pulse Width(3)

30

—

35

—

50

—

80

—

ns

tRSS

Reset Set-up Time(4)

30

—

35

—

50

—

80

—

ns

tRSR

Reset Recovery Time

10

—

10

—

15

—

20

—

ns

tRTC

Retransmit Cycle Time

40

—

45

—

65

—

100

—

ns

tRT

Retransmit Pulse Width(3)

30

—

35

—

50

—

80

—

ns

tRTS

Retransmit Set-up Time(4)

30

—

35

—

50

—

80

—

ns

tRTR

Retransmit Recovery Time

10

—

10

—

15

—

20

—

ns

tEFL

Reset to Empty Flag Low

—

40

—

45

—

65

—

100

ns

tHFH,FFH ResettoHalf-FullandFullFlagHigh

—

40

—

45

—

65

—

100

ns

tRTF

Retransmit Low to Flags Valid

—

40

—

45

—

65

—

100

ns

tREF

Read Low to Empty Flag Low

—

30

—

30

—

45

—

60

ns

tRFF

Read High to Full Flag High

—

30

—

30

—

45

—

60

ns

tRPE

Read Pulse Width after EF High

30

—

35

—

50

—

80

—

ns

tWEF

Write High to Empty Flag High

—

30

—

30

—

45

—

60

ns

tWFF

Write Low to Full Flag Low

—

30

—

30

—

45

—

60

ns

tWHF

Write Low to Half-Full Flag Low

—

40

—

45

—

65

—

100

ns

tRHF

Read High to Half-Full Flag High

—

40

—

45

—

65

—

100

ns

tWPF

Write Pulse Width after FF High

30

—

35

—

50

—

80

—

ns

tXOL

Read/Write to XO Low

—

30

—

35

—

50

—

80

ns

tXOH

Read/Write to XO High

—

30

—

35

—

50

—

80

ns

tXI

XI Pulse Width(3)

30

—

35

—

50

—

80

—

ns

tXIR

XI Recovery Time

10

—

10

—

10

—

10

—

ns

tXIS

XI Set-up Time

10

—

10

—

15

—

15

—

ns

NOTES:

1. Timings referenced as in AC Test Conditions

2. Military speed grades of 50ns and 80ns are only available for IDT7201LA.

3. Pulse widths less than minimum value are not allowed.

4. Values guaranteed by design, not currently tested.

5. Only applies to read data flow-through mode.

5

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