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IDT7281LA30SOGI8 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT7281LA30SOGI8 IDT
Integrated Device Technology IDT
DescriptionCMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9


IDT7281LA30SOGI8 Datasheet PDF : 14 Pages
First Prev 11 12 13 14
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
TABLE 1 — RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Mode
Inputs
RS
RT
XI
Internal Status
Read Pointer
Write Pointer
Reset
Retransmit
Read/Write
0
X
0
Location Zero
Location Zero
1
0
0
Location Zero
Unchanged
1
1
0
Increment(1)
Increment(1)
NOTE:
1. Pointer will increment if flag is HIGH.
Outputs
EF
FF
HF
0
1
1
X
X
X
X
X
X
TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Mode
Inputs
Internal Status
RS
FL
XI
Read Pointer
Write Pointer
Outputs
EF
FF
Reset First Device
Reset All Other Devices
Read/Write
0
0
(1)
Location Zero
Location Zero
0
1
(1)
Location Zero
Location Zero
1
X
(1)
X
X
0
1
0
1
X
X
NOTE:
1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,
XI = Expansion Input, HF = Half-Full Flag Output
W
D
FULL
RS
XO
R
FF
IDT EF
7200/
9
9
7201A/
9
Q
7202A FL
VCC
XI
XO
FF
IDT
EF
9
7200/
7201A/
7202A FL
EMPTY
FF
9
XI
XO
IDT
EF
7200/
7201A/
7202A
FL
XI
2678 drw16
Figure 14. Block Diagram of 768 x 9, 1,536 x 9, 3,072 x 9 FIFO Memory (Depth Expansion)
11
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DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load and empty data on a first-in/first-out basis. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. It also features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Military grade product is manufactured in compliance with MIL-STD-883, Class B.

FEATURES:
• First-In/First-Out dual-port memory
• 256 x 9 organization (IDT7200)
• 512 x 9 organization (IDT7201)
• 1,024 x 9 organization (IDT7202)
• Low power consumption
   — Active: 440mW (max.)
   —Power-down: 28mW (max.)
• Ultra high speed—12ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• 720x family is pin and functionally compatible from 256 x 9 to 64k x 9
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
• High-performance CEMOS™ technology
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-87531, 5962-89666, 5962-89863 and 5962-89536 are listed on this function
• Dual versions available in the TSSOP package. For more information, see IDT7280/7281/7282 data sheet
   IDT7280 = 2 x IDT7200
   IDT7281 = 2 x IDT7201
   IDT7282 = 2 x IDT7202

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