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IDT7281LA30DGB8 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT7281LA30DGB8 IDT
Integrated Device Technology IDT
DescriptionCMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9
IDT7281LA30DGB8 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
USAGE MODES:
WIDTH EXPANSION
Word width may be increased simply by connecting the corresponding
input control signals of multiple devices. Status flags (EF, FF and HF) can be
detected from any one device. Figure 13 demonstrates an 18-bit word width
by using two IDT7200/7201A/7202As. Any word width can be attained by
adding additional IDT7200/7201A/7202As (Figure 13).
BIDIRECTIONAL OPERATION
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT7200/7201A/7202As as shown in Figure 16. Both Depth Expansion and
Width Expansion may be used in this mode.
DATA FLOW-THROUGH
Two types of flow-through modes are permitted, a read flow-through
and write flow-through mode. For the read flow-through mode (Figure 17),
the FIFO permits a reading of a single word after writing one word of data into
an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the bus until the R line
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after tRHZ ns. The EF line would have a pulse showing temporary
deassertion and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing
of a single word of data immediately after reading one word of data from a
full FIFO. The R line causes the FF to be deasserted but the W line being LOW
causes it to be asserted again in anticipation of a new data word. On the rising
edge of W, the new word is loaded in the FIFO. The W line must be toggled
when FF is not asserted to write new data in the FIFO and to increment the write
pointer.
COMPOUND EXPANSION
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
(HALF-FULL FLAG) (HF)
WRITE (W)
9
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
IDT
9
7200/
7201A/
7202A
READ (R)
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
EXPANSION IN (XI)
Figure 12. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9 FIFO
2679 drw 14
18 9
DATA IN (D)
WRITE (W)
FULL FLAG (FF)
RESET (RS)
HF
9
IDT
7200/
7201A/
7202A
9
HF
IDT
7200/
7201A/
7202A
9
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
XI
XI
18
DATA OUT (Q)
2679 drw 15
Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion Mode
10
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DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load and empty data on a first-in/first-out basis. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. It also features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Military grade product is manufactured in compliance with MIL-STD-883, Class B.

FEATURES:
• First-In/First-Out dual-port memory
• 256 x 9 organization (IDT7200)
• 512 x 9 organization (IDT7201)
• 1,024 x 9 organization (IDT7202)
• Low power consumption
   — Active: 440mW (max.)
   —Power-down: 28mW (max.)
• Ultra high speed—12ns access time
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• 720x family is pin and functionally compatible from 256 x 9 to 64k x 9
• Status Flags: Empty, Half-Full, Full
• Auto-retransmit capability
• High-performance CEMOS™ technology
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-87531, 5962-89666, 5962-89863 and 5962-89536 are listed on this function
• Dual versions available in the TSSOP package. For more information, see IDT7280/7281/7282 data sheet
   IDT7280 = 2 x IDT7200
   IDT7281 = 2 x IDT7201
   IDT7282 = 2 x IDT7202

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