ISD5100 – SERIES
RAC Waveform During Digital Erase @ 8kHz Operation
INT is an open drain output pin. The ISD5100 Series interrupt pin goes LOW and stays LOW when an
Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or
OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ
STATUS instruction that will give a status byte out the SDA line.
XCLK (External Clock Input)
The external clock input for the ISD5100 Series product has an internal pull-down device. Normally,
the ISD5100 Series are operated at one of four internal rates selected for its internal oscillator by the
Sample Rate Select bits. If greater precision is required, the device can be clocked through the XCLK
pin at 4.096 MHz as described in section 7.4.3 on page 32.
Because the anti-aliasing and smoothing filters track the Sample Rate Select bits, one must, for
optimum performance, maintain the external clock at 4.096 MHz AND set the Sample Rate
Configuration bits to one of the four values to properly set the filters to the correct cutoff frequency as
described in section 7.4.3 on page 32. The duty cycle on the input clock is not critical, as the clock is
immediately divided by two internally. If the XCLK is not used, this input should be connected to VSSD.
External Clock Input Table
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Publication Release Date: October, 2003