ISD5102 View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

ISD5102

SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY

Winbond 

ISD5100 – SERIES

4. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS

FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS

FILTER STAGE.

5. Select the 6.4 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and

sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To

enable the 6.4 kHz sample rate, D2 must be set to ONE and D3 set to ZERO.

6. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and

S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6

respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to

select the LOW PASS FILTER (only) path.

In this mode, the elements of the original PASS THROUGH mode do not change. The sections of the

chip not required to add the record path remain powered down. In fact, CFG0 does not change and

remains

CFG0=0100 0100 0000 1011 (hex 440B).

CFG1 changes to

CFG1=0000 0000 1100 0101 (hex 00C5).

Since CFG0 is not changed, it is only necessary to load CFG1. Note that if only CFG0 was changed, it

would be necessary to load both registers.

7.3.9. Memo Record

The Memo Record mode sets the chip up to record from the local microphone into the chip’s Multilevel

Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down

and is not active in this mode. The path to be used is microphone input to AGC amplifier, then through

the INPUT SOURCE MUX to the SUM1 SUMMING amplifier. From there the path goes through the

FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL

STORAGE ARRAY. In this instance, we will select the 5.3 kHz sample rate. The rest of the chip may

be powered down.

1. Power up the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier. This

is bit D0 of CFG1 and must be set to ZERO to power up this stage.

2. Select the AGC amplifier through the INPUT SOURCE MUX—Bit INS0 controls the state of

the INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the

AGC amplifier.

3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1

control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of

CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the

INPUT SOURCE MUX (only) path.

4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the

state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the

SUM1 SUMMING amplifier path.

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Publication Release Date: October, 2003

Revision 0.2

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