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I5216 View Datasheet(PDF) - Winbond

Part NameDescriptionManufacturer
I5216 8 TO 16 MINUTE VOICE RECORD/PLAYBACK SYSTEM WITH INTEGRATED CODEC Winbond
Winbond Winbond
I5216 Datasheet PDF : 83 Pages
First Prev 41 42 43 44 45 46 47 48 49 50 Next Last
I5216 SERIES
Advanced Information
PRELIMINARY
Master Clock Input Table for ChipCorder Section
FMCLK
13.824 MHz
FLD1 FLD0 CKD2 CKDV Sample Rate
0
0
0
0
8.0 kHz
20.48 MHz
0
0
0
1
8.0 kHz
27.648 MHz
40.96 MHz
13.824 MHz
20.48 MHz
27.648 MHz
40.96 MHz
13.824 MHz
20.48 MHz
27.648 MHz
40.96 MHz
13.824 MHz
20.48 MHz
27.648 MHz
40.96 MHz
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
8.0 kHz
8.0 kHz
6.4 kHz
6.4 kHz
6.4 kHz
6.4 kHz
5.3 kHz
5.3 kHz
5.3 kHz
5.3 kHz
4.0 kHz
4.0 kHz
4.0 kHz
4.0 kHz
Filter Knee
3.7 kHz
3.7 kHz
3.7 kHz
3.7 kHz
2.9 kHz
2.9 kHz
2.9 kHz
2.9 kHz
2.5 kHz
2.5 kHz
2.5 kHz
2.5 kHz
1.8 kHz
1.8 kHz
1.8 kHz
1.8 kHz
Because the anti-aliasing and smoothing filters track the Sample Rate Select bits, one must, for
optimum performance, maintain the external clock at one of the four possible frequencies shown in the
table for Analog Structure (Right Half) description on page 36 AND set the Sample Rate Configuration
bits to one of the four values in order to properly set the filters to their correct cutoff frequency as
described in Analog Structure (Right Half) description on page 36. The duty cycle on the input clock is
not critical when CKD2 is set to ONE, as the clock is immediately divided by two (internally). If the
MCLK is not used, this input should be connected to VSSD.
A0, A1 (Address Pins)
These two pins are normally strapped for the desired address that the Winbond I5216 will have on the
I2C serial interface. If there are four of these devices on the bus, then each must be strapped
differently in order to allow the master device to address them individually. The possible addresses
range from 80h to 87h, depending upon whether the device is being written to, or read from, by the
host.
The Winbond I5216 has a 7-bit slave address of which only A0 and A1 are pin programmable. The
eighth bit (LSB) is the R/W bit. Thus, the address will be 1000 0xy0 or 1000 0xy1
Publication Release Date: November 30, 2001
- 47
Revision A1
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