1. Select the CODEC path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of the
SUM1 MUX. These are bits D9 and D10, respectively, of CFG1 and they should be set to the state
where both D9 and D10 are ZERO to select the CODEC path.
2. Select the SUM1 MUX input (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1 control
the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of CFG1 and
they should be set to the state where D7 is ONE and D8 is ZERO to select the SUM1 MUX (only)
3. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the state
of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUM-
MING amplifier path.
4. Deselect the signal compression-Bit AMT0 controls the signal compression. This is bit D7 of CFG0
and it must be set to ZERO.
5. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
6. Select the 6.4 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and sample
rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 6.4
kHz sample rate, D2 must be set to ONE and D3 set to ZERO.
7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6, respectively, of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
The configuration settings in the call record mode are:
CFG0=0100 0100 0000 1011 (hex 440B).
CFG1=0000 0000 1100 0101 (hex 00C5).
CFG2=0000 0000 0100 0000 (hex 0040).
The Memo Record mode sets the chip up to record from the local microphone into the chip’s Multilevel
Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down
since they are not active in this mode. The path to be used is microphone input to AGC amplifier, then
through to the INPUT SOURCE MUX, to the SUM1 SUMMING amplifier. From there, the path goes
through the FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the
MULTILEVEL STORAGE ARRAY. In this example, we will select the 5.3 kHz sample rate. The rest of
the chip may be powered down.
1. Power up the AGC amplifier Bit AGPD controls the power up state of the AGC amplifier. This is bit
D0 of CFG1 and must be set to ZERO to power up this stage.
2. Select the AGC amplifier through the INPUT SOURCE MUX—Bit INS0 controls the state of the
INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the AGC am-
Publication Release Date: November 30, 2001