I5216P View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

I5216P

8 TO 16 MINUTE VOICE RECORD/PLAYBACK SYSTEM WITH INTEGRATED CODEC

Winbond 

I5216 SERIES

Advanced Information

PRELIMINARY

FEED THROUGH MODE

The previous examples were dependent upon the device already being powered up and the various

paths being set through the device for the desired operation. To set up the device for the various paths

requires loading the three 16-bit Configuration Registers with the correct data. For example, in the

Feed Through Mode, the device only needs to be powered up and a few paths selected. This mode

enables the I5216 to connect to a cellular or cordless baseband phone chip set without affecting the

audio source or destination. There are two paths involved: the transmit path and the receive path. The

transmit path connects the Winbond chip’s microphone source through to the digital audio input on the

baseband chip set. The receive path connects the baseband chip set’s digital output through to the

speaker driver on the Winbond chip. This allows the Winbond chip to substitute for Analog to Digital

and Digital to Analog conversion, and incidentally gain access to the audio, both to and from the

baseband chip set.

To setup the environment described above, a series of commands need to be sent to the I5216. First,

the chip needs to be powered up as described in Power-Up Sequence on page 25. Then the

Configuration Registers need to be filled with the specific data to connect the desired paths. In the

case of the Feed Through Mode, most of the chip can remain powered down. The Feed Through

Mode diagram illustrates the affected paths

To select the Feed Through mode, the following control bits must be configured in the I5216 configura-

tion register

To set up the transmit path:

1. Select the FTHRU path through the CODEC INPUT MUX—Bits CDI1 and CDI0 control the

state of the CODEC INPUT MUX. These are the D6 and D5 bits, respectively, of Configuration

Register 0 (CFG0) and they should be set to ONE and ZERO, respectively, to select the

FTHRU path.

2. Power up the ADC—Bit ADPD controls the power up state of ADC. This is bit D0 of CFG2 and

it should be a ZERO to power up the ADC.

3. Set the CODEC input gain. The input gain setting will depend on the input level at the MIC+/-

pins and can be set by the CODEC INPUT GAIN Bits CIG2, CIG1 and CIG0. These are the

D15, D14 and D13 bits, respectively, of Configuration Register 0 (CFG0). The input gain can

be set according to the following table. (Table A)

4. Enable the High Pass Filter, if desired, in the low sample rate mode. This can be done by

setting bit HPF0 to ONE. This is bit D6 of CFG2.

5. Select the low or high sample rate mode by setting bit HSR0. This is bit D5 of CFG2. HSR0

needs to be set to ONE for the high sample rate mode.

6. Set the MUTE bit if desired. This bit can be set temporarily to reduce power up ‘pops’ or to set

the system on hold. This bit is D7 of CFG2 and needs to be set to ONE in order to mute the

signal.

7. Set the digital data format through bits LAW1 and LAW0. These are bits D3 and D2 of CFG2,

respectively. The data format can be chosen according to the following table. (Table B).

8. Set the interface mode to PCM-interface by setting bit I2S0 to ZERO. This will also enable full

duplex mode. This bit is bit D4 of CFG2.

9. Set the Master Clock division ratios as described in Set Master Clock Division Ratio on page

25.

Publication Release Date: November 30, 2001

- 27

Revision A1

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