HT45F4M View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
Manufacturer
HT45F4M Datasheet PDF : 138 Pages
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HT45F4M
Lithium Battery Backup Power ASSP MCU
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name FSYSON —
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
x
0
0
Bit 7
Bit 6~3
Bit 2
Bit 1
Bit 0
FSYSON: fSYS Control in IDLE Mode
Describe elsewhere.
“—”: Unimplemented, read as 0
LVRF: LVR function reset flag
Describe elsewhere.
LRF: LVR Control register software reset flag
Describe elsewhere.
WRF: WDT Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the application
program. Note that this bit can only be cleared to 0 by the application program.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear WDT instruction will not be executed in
the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are
five bits, WE4~WE0, in the WDTC register to enable the WDT function. When the WE4~WE0 bits
value is equal to 01010B or 10101B, the WDT function is enabled. However, if the WE4~WE0 bits
are changed to any other values except 01010B and 10101B, which is caused by the environmental
noise, it will reset the microcontroller after 2~3 LIRC clock cycles.
WE4 ~ WE0 Bits
WDT Function
01010B or 10101B
Enable
Any other value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value is written into the WE4~WE0 bit filed except
01010B and 10101B, the second is using the Watchdog Timer software clear instructions and the
third is via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single “CLR WDT” instruction to clear the WDT.
The maximum time-out period is when the 218 division ratio is selected. As an example, with a 32
kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration.
Rev. 1.10
42
January 15, 2013
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