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GLT61132-40TQ View Datasheet(PDF) - G-Link Technology

Part NameGLT61132-40TQ G-Link
G-Link Technology  
Description256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT


GLT61132-40TQ Datasheet PDF : 17 Pages
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G-LINK
GLT440L16
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug. 2000 (Rev.1.1)
Truth Table: GLT440L16
Function
RAS
Stanby
H
Read: Word
L
Read: Lower Byte
L
Read: Upper Byte
L
Write: Word(Early
L
Write)
Write: Lower Byte
L
(Early)
Write: Upper Byte
L
(Early)
Read Write
L
EDO-Page- 1st Cycle
L
Mode Read 2nd Cycle
L
CASL CASH WE
H
H
X
L
L
H
L
H
H
H
L
H
L
L
L
OE ADDRESS
DQs
Notes
X
High-Z
L ROW/COL Data Out
L ROW/COL Lower Byte,Data-Out
Upper Byte,High-Z
L ROW/COL Lower Byte,High-Z
Upper Byte,Data-Out
X ROW/COL Data-In
L
H
L
X ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
H
L
L
X ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
L
L HL LH ROW/COL Data-Out,Data-In
1,2
HL HL H
L ROW/COL Data-Out
2
HL HL H
L
COL Data-Out
2
EDO-Page- 1st Cycle
L
HL HL L
X ROW/COL Data-In
2
Mode Write 2nd Cycle
L
HL HL L
X
COL Data-In
2
EDO-Page- 1st Cycle
Mode Read-
L
HL HL HL LH ROW/COL Data-Out,Data-In
1,2
Write
2nd Cycle
L
HL HL HL LH
COL Data-Out,Data-In
1,2
Hidden
Read
LHL L
L
H
L ROW/COL Data-Out
2
Refresh
Write
LHL L
L
H
L ROW/COL Data-In
2
RAS -Only Refresh
L
H
H
X
X
ROW High-Z
CBR Refresh
HL
L
L
X
X
High-Z
3
Notes:
1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active).
2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active ( UCAS or LCAS ).
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-4-
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E, RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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Description :
The GLT440L16 is a 262,144 x 16 bit high-performance CMOS dynamic random access memory. The GLT44016 offers Fast Page mode with Extended Data Output, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT440L16 has symmetric address and accepts 512-cycle refresh in 8ms interval All inputs are TTL compatible. EDO Page Mode operation allows random access up to 512 x 16 bits within a page, with cycle time as short as 14ns.
The GLT440L16 is best suited for graphics, and DSP applications requiring high performance memories.

Features :
* 262,144 words by 16 bits organization.
* Fast access time and cycle time.
* Dual CAS Input.
* Low power dissipation.
* Read-Modify-Write, RAS-Only Refresh, CAS -Before-RAS Refresh, Hidden Refresh and Test Mode Capability.
* 512 refresh cycles per 8ms.
* Available in 40-Pin 400 mil SOJ and 40/44 Pin TSOP(II)
* Single +3.3V±10% Power Supply.
* All inputs and Outputs are TTL compatible.
* Extended Data-Out(EDO) Page Mode operation.

 

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