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AD14060BF-4 데이터 시트보기 (PDF) - Analog Devices

부품명상세내역제조사
AD14060BF-4 Quad-SHARC® DSP Multiprocessor Family ADI
Analog Devices ADI
AD14060BF-4 Datasheet PDF : 44 Pages
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AD14060/AD14060L
OUTPUT DRIVE CURRENTS
Figure 26 shows typical I-V characteristics for the output drivers
of the ADSP-2106x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
120
100
80
HIGH LEVEL DRIVE
(P DEVICE)
60
40
20
0
–20
–40
–60
–80
–100
–120
LOW LEVEL DRIVE
(N DEVICE)
–140
–160
0
1
2
3
4
5
SOURCE VOLTAGE – V
Figure 26. ADSP-2106x Typical Drive Currents (VDD = 5 V)
POWER DISSIPATION
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved. Inter-
nal power dissipation is calculated in the following way:
PINT = IDDIN × VDD
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
– the number of output pins that switch during each cycle (O)
– the maximum frequency at which they can switch (f)
– their load capacitance (C)
– their voltage swing (VDD)
and is calculated by:
PEXT = O × C × VDD2 × f
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2tCK). The write strobe
can switch every cycle at a frequency of 1/tCK. Select pins switch
at 1/(2tCK), but selects can switch on each cycle.
Example:
Estimate PEXT with the following assumptions:
–A system with one bank of external data memory RAM (32-bit)
–Four 128K × 8 RAM chips are used, each with a load of 10 pF
–External data memory writes occur every other cycle, a rate
–of 1/(4tCK), with 50% of the pins switching
–The instruction cycle rate is 40 MHz (tCK = 25 ns) and
–VDD = 5.0 V.
The PEXT equation is calculated for each class of pins that can
drive:
Pin
Type
# of
Pins
Address 15
MS0
1
WR
1
Data
32
ADRCLK 1
%
Switching ؋ C
50
× 55 pF
0
× 55 pF
× 55 pF
50
× 25 pF
× 15 pF
؋f
؋ VDD2 = PEXT
× 20 MHz × 25 V
× 20 MHz × 25 V
× 40 MHz × 25 V
× 20 MHz × 25 V
40 MHz × 25 V
= 0.206 W
= 0.00 W
= 0.055 W
= 0.200 W
= 0.015 W
PEXT (5 V) = 0.476 W
PEXT (3.3 V) = 0.207 W
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
PTOTAL = PEXT + (IDDIN2 × 5.0 V )
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Also note that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by V is dependent on the capacitive load, CL, and
the load current, IL. This decay time can be approximated by
the following equation:
tDECAY
= CL V
IL
The output disable time, tDIS, is the difference between tMEASURED
and tDECAY as shown in Figure 27. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and
IL, and with V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time, tENA, is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 27). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
V to be the difference between the ADSP-2106x’s output
voltage and the input threshold for the device requiring the hold
time. A typical V will be 0.4 V. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
REV. A
–37–
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