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AD14060BF-4 데이터 시트보기 (PDF) - Analog Devices

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AD14060BF-4 Quad-SHARC® DSP Multiprocessor Family ADI
Analog Devices ADI
AD14060BF-4 Datasheet PDF : 44 Pages
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AD14060/AD14060L
DATA RECEIVE– INTERNAL CLOCK
DRIVE
EDGE
tSCLKIW
RCLK
tDFSE
tHFSE
tSFSI
RFS
SAMPLE
EDGE
tHFSI
tSDRI
tHDRI
DR
DATA RECEIVE– EXTERNAL CLOCK
DRIVE
EDGE
tSCLKW
RCLK
tDFSE
tHFSE
tSFSE
SAMPLE
EDGE
tHFSE
RFS
tSDRE
tHDRE
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DRIVE
EDGE
tSCLKIW
TCLK
tDFSI
tHFSI
tSFSI
TFS
tHDTI tDDTI
SAMPLE
EDGE
tHFSI
DT
DATA TRANSMIT– EXTERNAL CLOCK
DRIVE
EDGE
tSCLKW
TCLK
tDFSE
tHFSE
tSFSE
SAMPLE
EDGE
tHFSE
TFS
tHDTE tDDTE
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
TCLK (EXT)
DT
TCLK (INT)
DRIVE
EDGE
tDDTEN
DRIVE
EDGE
tDDTIN
DT
TCLK / RCLK
DRIVE
EDGE
tDDTTE
TCLK / RCLK
DRIVE
EDGE
tDDTTI
CLKIN
TCLK, RCLK
TFS, RFS, DT
TCLK (INT)
RCLK (INT)
tDPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
tDCLK
LOW TO HIGH ONLY
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
CLKIN
tSTFSCK
tHTFSCK
TFS (EXT)
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR
MESH MULTIPROCESSING.
Figure 24. Serial Ports
REV. A
–35–
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