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AD14060BF-4 데이터 시트보기 (PDF) - Analog Devices

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AD14060BF-4 Quad-SHARC® DSP Multiprocessor Family ADI
Analog Devices ADI
AD14060BF-4 Datasheet PDF : 44 Pages
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AD14060/AD14060L
Serial Ports
Parameter
5V
Min
External Clock
Timing Requirements:
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
4
tHFSE
TFS/RFS Hold After TCLK/RCLK1, 2
4.5
tSDRE
Receive Data Setup Before RCLK1
2
tHDRE
Receive Data Hold After RCLK1
4.5
tSCLKW TCLK/RCLK Width
9.5
tSCLK
TCLK/RCLK Period
tCK
Internal Clock
Timing Requirements:
tSFSI
tHFSI
tSDRI
tHDRI
TFS Setup Before TCLK1; RFS Setup Before RCLK1 9
TFS/RFS Hold After TCLK/RCLK1, 2
1
Receive Data Setup Before RCLK1
4
Receive Data Hold After RCLK1
3
External or Internal Clock
Switching Characteristics:
tDFSE
RFS Delay After RCLK (Internally Generated RFS)3
tHFSE
RFS Hold After RCLK (Internally Generated RFS)3 3
External Clock
Switching Characteristics:
tDFSE
tHFSE
tDDTE
tHDTE
TFS Delay After TCLK (Internally Generated TFS)3
TFS Hold After TCLK (Internally Generated TFS)3 3
Transmit Data Delay After TCLK3
Transmit Data Hold After TCLK3
5
Internal Clock
Switching Characteristics:
tDFSI
TFS Delay After TCLK (Internally Generated TFS)3
tHFSI
TFS Hold After TCLK (Internally Generated TFS)3
tDDTI
tHDTI
Transmit Data Delay After TCLK3
Transmit Data Hold After TCLK3
tSCLKIW TCLK/RCLK Width
–1.5
0
(SCLK/2) – 2
Enable and Three-State
Switching Characteristics:
tDDTEN Data Enable from External TCLK3
3.5
tDDTTE Data Disable from External TCLK3
tDDTIN Data Enable from Internal TCLK3
0
tDDTTI Data Disable from Internal TCLK3
tDCLK
TCLK/RCLK Delay from CLKIN
tDPTR
SPORT Disable After CLKIN
External Late Frame Sync
Switching Characteristics:
tDDTLFSE Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 04
tDDTENFS Data Enable from late FS or MCE = 1, MFD = 04
3.0
Max
14
14
17
5
8
(SCLK/2) + 2
11.5
3
23 + 3DT/8
18
13
3.3 V
Min
Max
Units
4
ns
4.5
ns
2
ns
4.5
ns
9
ns
tCK
ns
9
ns
1
ns
4
ns
3
ns
14
ns
3
ns
14
ns
3
ns
17
ns
5
ns
5
ns
–1.5
ns
8
ns
0
ns
(SCLK/2) – 2.5 (SCLK/2) + 2.5 ns
4
ns
11.5
ns
0
ns
3
ns
23 + 3DT/8 ns
18
ns
13.8
ns
3.5
ns
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
NOTES
1Referenced to sample edge.
2RFS hold after RCK when MCE = 1, MFD = 0 is 0.5 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0.5 ns minimum from drive edge.
3Referenced to drive edge.
4MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.
REV. A
–33–
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