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AD14060BF-4 데이터 시트보기 (PDF) - Analog Devices

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AD14060BF-4 Quad-SHARC® DSP Multiprocessor Family ADI
Analog Devices ADI
AD14060BF-4 Datasheet PDF : 44 Pages
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AD14060/AD14060L
TRANSMIT
CLKIN
LCLK 1x
OR
LCLK 2x
tDLCLK
tLCLKTWH
tLCLKTWL
tDLDCH
tHLDCH
LAST NIBBLE
TRANSMITTED
FIRST NIBBLE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LDAT(3:0)
LACK (IN)
OUT
tSLACH
tHLACH
tDLACLK
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
RECEIVE
CLKIN
LCLK 1x
OR
LCLK 2x
LDAT(3:0)
LACK (OUT)
tDLAHC
tLCLKRWH
tLCLKIW
tSLDCL
IN
tHLDCL
tLCLKRWL
tDLALC
LACK GOES LOW ONLY AFFTER THE SECOND NIBBLE IS RECEIVED.
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
CLKIN
LCLK
LDAT(3:0)
LACK
tENDLK
tTDLK
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
LINK PORT INTERRUPT SETUP TIME
CLKIN
LCLK
LACK
tSLCK
tHLCK
Figure 22. Link Ports
–32–
REV. A
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