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AD14060BF-4 데이터 시트보기 (PDF) - Analog Devices

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AD14060BF-4 Quad-SHARC® DSP Multiprocessor Family ADI
Analog Devices ADI
AD14060BF-4 Datasheet PDF : 44 Pages
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AD14060/AD14060L
Link Ports: 1 × CLK Speed Operation
Parameter
Receive
Timing Requirements:
tSLDCL
tHLDCL
tLCLKIW
tLCLKRWL
tLCLKRWH
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (1 × Operation)
LCLK Width Low
LCLK Width High
5V
Min
Max
3.5
3
tCK
6
5
3.3 V
Min
Max
3
3
tCK
6
5
Units
ns
ns
ns
ns
ns
Switching Characteristics:
tDLAHC
tDLALC
tENDLK
tTDLK
LACK High Delay After CLKIN High
LACK Low Delay After LCLK High1
LACK Enable from CLKIN
LACK Disable from CLKIN
18 + DT/2
–3
5 + DT/2
29.5 + DT/2
13.5
21 + DT/2
18 + DT/2 29.5 + DT/2 ns
–3
13.5
ns
5 + DT/2
ns
21 + DT/2
ns
Transmit
Timing Requirements:
tSLACH
LACK Setup Before LCLK High
18
tHLACH
LACK Hold After LCLK High
–7
20
ns
–7
ns
Switching Characteristics:
tDLCLK
LCLK Delay After CLKIN (1 × Operation)
tDLDCH
Data Delay After LCLK High
tHLDCH
Data Hold After LCLK High
tLCLKTWL
LCLK Width Low
tLCLKTWH LCLK Width High
tDLACLK
LCLK Low Delay After LACK High
tENDLK
LDAT, LCLK Enable After CLKIN
tTDLK
LDAT, LCLK Disable After CLKIN
–3
(tCK/2) – 2
(tCK/2) – 2
(tCK/2) + 8.5
5 + DT/2
16.5
3.5
(tCK/2) + 2
(tCK/2) + 2
(3 × tCK/2) + 17.5
21 + DT/2
–3
(tCK/2) – 1
(tCK/2) – 1.25
(tCK/2) + 8
5 + DT/2
17.5
ns
3
ns
ns
(tCK/2) + 1.25 ns
(tCK/2) + 1
ns
(3 × tCK/2) + 18 ns
ns
21 + DT/2
ns
Link Port Service Request Interrupts:
1 × and 2 × Speed Operations
Timing Requirements:
tSLCK
tHLCK
LACK/LCLK Setup Before CLKIN Low2 10
LACK/LCLK Hold After CLKIN Low2
2.5
10
ns
2.5
ns
NOTES
1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
2Only required for interrupt recognition in the current cycle.
–30–
REV. A
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