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AD14060BF-4 데이터 시트보기 (PDF) - Analog Devices

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AD14060BF-4 Quad-SHARC® DSP Multiprocessor Family ADI
Analog Devices ADI
AD14060BF-4 Datasheet PDF : 44 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
AD14060/AD14060L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
B Grade
Min
Max
K Grade
Min
Max
Units
VDD
TCASE
Supply Voltage (5 V)
Supply Voltage (3.3 V)
Case Operating Temperature
4.75
5.25
4.75
5.25
V
3.15
3.6
3.15
3.6
V
–40
+100
0
+85
°C
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Parameter
Case Test
Temp Level Test Condition
5V
Min Typ Max
3.3 V
Min Typ Max
Units
VIH1
VIH2
VIL
VOH
VOL
IIH
IIL
IILP
IILPX4
IOZH
IOZL
IOZHP
IOZLC
IOZLA
High Level Input Voltage1
High Level Input Voltage2
Low Level Input Voltage1, 2
High Level Output Voltage3, 4
Low Level Output Voltage3, 4
High Level Input Current5, 6, 7
Low Level Input Current5
Low Level Input Current6
Low Level Input Current7
Three-State Leakage Current8, 9, 10, 14
Three-State Leakage Current8, 11
Three-State Leakage Current11
Three-State Leakage Current12
Three-State Leakage Current13
IOZLAR
IOZLS
IOZLSX4
IDDIN
IDDIDLE
CIN
Three-State Leakage Current10
Three-State Leakage Current9
Three-State Leakage Current14
Supply Current (Internal)15
Supply Current (Idle)16
Input Capacitance17, 18
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full I
Full IV
Full I
+25°C V
@ VDD = max
2.0
@ VDD = max
2.2
@ VDD = min
@ VDD = min, IOH = –2.0 mA4 4.1
@ VDD = min, IOL = 4.0 mA4
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 1.5 V (5 V),
2 V (3.3 V)
VDD + 0.5 2.0
VDD + 0.5 2.2
0.8
2.4
0.4
10
10
150
600
10
10
350
1.5
350
VDD + 0.5 V
VDD + 0.5 V
0.8
V
V
0.4
V
10
µA
10
µA
150
µA
600
µA
10
µA
10
µA
350
µA
1.5
mA
350
µA
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
tCK = 25 ns, VDD = max
VDD = max
4.2
150
600
1.4 3.4
800
15
4.2
mA
150
µA
600
µA
1.0 2.2
A
760
mA
15
pF
EXPLANATION OF TEST LEVELS
Test Level
I
100% Production Tested19.
II 100% Production Tested at +25°C, and Sample Tested at Specified Temperatures.
III Sample Tested Only.
IV Parameter is guaranteed by design and analysis, and characterization testing on discrete SHARCs.
V Parameter is typical value only.
VI All devices are 100% production tested at +25°C; sample tested at temperature extremes.
NOTES
1 Applies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQy2-0, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2,
BR6-1, RPBA, CPAy, TFS0, TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS,
TDI, TCK, HBR, DR0, DRy1, TCLK0, TCLKy1, RCLK0, RCLKy1.
2 Applies to input pins: CLKIN, RESET, TRST.
3 Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0 RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy, HBG,
REDY, DMAG1, DMAG2, BR6-1, CPAy, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1 LyxDAT 3-0, LyxCLK, LyxACK,
BMSA, BMSBCD, TDO, EMU.
4 See Output Drive Currents for typical drive current capabilities.
5 Applies to input pins: SBTS, IRQy2-0, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.
6 Applies to input pins with internal pull-ups: DR0, DRy1, TDI.
7Applies to bussed input pins with internal pull-ups: TRST, TMS.
8 Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2,
BMSA, BMSBCD, TDO, EMU. (Note that ACK is pulled up internally with 2 kduring reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-
2106x is not requesting bus mastership. HBG AND EMU are not tested for leakage current.)
9 Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.
10 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-2106x is not requesting bus mastership.)
11 Applies to three-statable pins with internal pull-downs: LyxDAT3-0, LyxCLK, LyxACK.
12 Applies to CPAy pin.
13Applies to ACK pin when keeper latch enabled.
14Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.
15 Applies to VDD pins. Conditions of operation: each processor executing radix-2 FFT butterfly with instruction in cache, one data operand fetched from each internal
memory block, and one DMA transfer occurring from/to internal memory at t CK = 25 ns.
16 Applies to VDD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17Applies to all signal pins.
18Guaranteed but not tested.
19Link and Serial Ports: All are 100% tested at die level prior to assembly. All are 100% ac tested at module level; Link-4 and Serial-0 are also dc tested at the module
level. See Timing Specifications.
Specifications subject to change without notice.
–14–
REV. A
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