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AD14060BF-4 데이터 시트보기 (PDF) - Analog Devices

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AD14060BF-4 Quad-SHARC® DSP Multiprocessor Family ADI
Analog Devices ADI
AD14060BF-4 Datasheet PDF : 44 Pages
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operations such as starting, stopping and single-stepping mul-
tiple ADSP-2106xs in a synchronous manner. If you do not
need these operations to occur synchronously on the multiple
processors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and CLKIN
is connected, clock skew between the AD14060/AD14060L and
the CLKIN pin on the EZ-ICE header must be minimal. If the
skew is too large, synchronous operations may be off by one
cycle between processors. For synchronous multiprocessor
operation TCK, TMS, CLKIN and EMU should be treated as
critical signals in terms of skew, and should be laid out as short
AD14060/AD14060L
as possible on your board. If TCK, TMS and CLKIN are driv-
ing a large number of ADSP-2106xs (more than eight) in your
system, then treat them as a “clock tree” using multiple drivers
to minimize skew. (See Figure 8 JTAG Clock Tree and Clock
Distribution in the “High Frequency Design Considerations”
section of the ADSP-2106x User’s Manual).
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
TDI TDO
TDI TDO
TDI TDO
5k
*
TDI
EMU
TCK
TMS
TRST
TDO
CLKIN
TDI TDO TDI TDO
TDI TDO
5k
*
*OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
EMU
Figure 8. JTAG Clocktree for Multiple ADSP-2106x Systems
SYSTEM
CLKIN
REV. A
–13–
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