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HI-8581CJI-10 View Datasheet(PDF) - Holt Integrated Circuits

Part NameHI-8581CJI-10 HOLTIC
Holt Integrated Circuits HOLTIC
DescriptionARINC 429 Transmitter with Line Driver and Dual Receivers


HI-8581CJI-10 Datasheet PDF : 15 Pages
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HI-8581, HI-8589
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either TXA(OUT) or TXB(OUT). The 31 bits in
the data transmission shift register are presented sequentially to
the outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
SELF TEST
If the BD05 control word bit is set low, the digital outputs of the
transmitter are internally connected to the logic inputs of the
receivers, bypassing the analog bus interface circuitry. Data to
Receiver 1 is as transmitted and data to Receiver 2 is the
complement. All data transmitted during self test is also present
on the TXA(OUT) and TXB(OUT) line driver outputs.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
1. The received data may be overwritten if not retrieved
within one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
Both bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go
low until TX/R, transmitter ready flag, goes high. Otherwise,
one ARINC word is lost during transmission.
31 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
BIT BD12
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
LINE DRIVER
TXA(OUT)
TXB(OUT)
8 X 31 FIFO
WORD CLOCK
ADDRESS
LOAD
DATA BUS
FIGURE 3. TRANSMITTER BLOCK DIAGRAM
BIT
AND
WORD GAP
COUNTER
START
SEQUENCE
WORD COUNTER
AND
FIFO CONTROL
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
DATA
CLOCK
DATA CLOCK
DIVIDER
CONTROL BIT
BD13
TX/R
ENTX
PL1
PL2
CLK
TX CLK
HOLT INTEGRATED CIRCUITS
5
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GENERAL DESCRIPTION
The HI-8581 and HI-8589 from Holt Integrated Circuits are silicon gate CMOS devices for interfacing a 16-bit parallel data bus directly to the ARINC 429 serial bus. Both devices provide two receivers, an independent transmitter and line driver capability in a single package. The receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol. The transmitter section provides the ARINC 429 communication protocol and the line driver circuits provide the ARINC 429 output levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The data bus interfaces with CMOS and TTL.
The HI-8581 has 37.5 ohms in series with each line driver output. The HI-8589 provides the option to bypass most of the internal output resistance so that external series resistance may be added for lighting protection and still match the 75 ohm characteristic impedance of the ARINC bus.

FEATURES
• ARINC specification 429 compliant
• Direct receiver and transmitter interface to ARINC bus in a single device
• 16-Bit parallel data bus
• Timing control 10 times the data rate
• Selectable data clocks
• Receiver error rejection per ARINC 429 standard
• Automatic transmitter data timing
• Parity functions
• Low power
• Self test mode
• Industrial & extended temperature ranges

 

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