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HI-8581CJI-10 View Datasheet(PDF) - Holt Integrated Circuits

Part NameHI-8581CJI-10 HOLTIC
Holt Integrated Circuits HOLTIC
DescriptionARINC 429 Transmitter with Line Driver and Dual Receivers
HI-8581CJI-10 Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PIN DESCRIPTION
HI-8581, HI-8589
SIGNAL
VCC
V+
V-
429DI1 (A)
429DI1 (B)
429DI2 (A)
429DI2 (B)
D/R1
D/R2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
FUNCTION
POWER
POWER
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
I/O
I/O
I/O
I/O
I/O
TX/R
OUTPUT
PL1
PL2
TXA(OUT)
TXB(OUT)
ENTX
CWSTR
CLK
TX CLK
MR
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
DESCRIPTION
+5V ±5%
+9.5V to +10.5V
-9.5V to -10.5V
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
Receiver 2 data ready flag
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if EN1 is high
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0V
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Line driver output - A side
Line driver output - B side
Enable Transmission
Clock for control word register
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
2
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