HIN239BY View Datasheet(PDF) - Harris Semiconductor
Part Name
Description
Manufacturer
HIN239BY Datasheet PDF : 14 Pages
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HIN230 thru HIN241
VCC
GND
VOLTAGE DOUBLER
S1
C1+
S2
+
- C1
S3
C1-
S4
V+ = 2VCC
VOLTAGE INVERTER
S5
C2+
S6
+
- C3
VCC
GND
S7
+
- C2
C2-
S8
+
- C4
GND
V- = -(V+)
RC
OSCILLATOR
FIGURE 1. CHARGE PUMP
Detailed Description
The HIN230 thru HIN241 family of RS-232 transmitters/receiv-
ers are powered by a single +5V power supply (except HIN-231
and HIN239), feature low power consumption, and meet all ElA
RS-232C and V.28 specifications. The circuit is divided into
three sections: the charge pump, transmitter, and receiver.
Charge Pump
An equivalent circuit of the charge pump is illustrated in Figure
1. The charge pump contains two sections: the voltage dou-
bler and the voltage inverter. Each section is driven by a two
phase, internally generated clock to generate +10V and -10V.
The nominal clock frequency is 16kHz. During phase one of
the clock, capacitor C1 is charged to VCC. During phase two,
the voltage on C1 is added to VCC, producing a signal across
C3 equal to twice VCC. During phase one, C2 is also charged
to 2VCC, and then during phase two, it is inverted with respect
to ground to produce a signal across C4 equal to -2VCC. The
charge pump accepts input voltages up to 5.5V. The output
impedance of the voltage doubler section (V+) is approxi-
mately 200Ω, and the output impedance of the voltage
inverter section (V-) is approximately 450Ω. A typical applica-
tion uses 1µF capacitors for C1-C4, however, the value is not
critical. Increasing the values of C1 and C2 will lower the out-
put impedance of the voltage doubler and inverter, increasing
the values of the reservoir capacitors, C3 and C4, lowers the
ripple on the V+ and V- supplies.
During shutdown mode (HIN230, 236, 240 and 241), SHUT-
DOWN control line set to logic “1”, the charge pump is
turned off, V+ is pulled down to VCC, V- is pulled up to GND,
and the supply current is reduced to less than 10µA. The
transmitter outputs are disabled and the receiver outputs are
placed in the high impedance state.
Transmitters
The transmitters are TTL/CMOS compatible inverters which
translate the inputs to RS-232 outputs. The input logic thresh-
old is about 26% of VCC, or 1.3V for VCC = 5V. A logic 1 at the
input results in a voltage of between -5V and V- at the output,
and a logic 0 results in a voltage between +5V and (V+ -0.6V).
Each transmitter input has an internal 400kΩ pullup resistor
so any unused input can be left unconnected and its output
remains in its low state. The output voltage swing meets the
RS-232C specifications of ±5V minimum with the worst case
conditions of: all transmitters driving 3kΩ minimum load
impedance, VCC = 4.5V, and maximum allowable operating
temperature. The transmitters have an internally limited output
slew rate which is less than 30V/µs. The outputs are short cir-
cuit protected and can be shorted to ground indefinitely. The
powered down output impedance is a minimum of 300Ω with
±2V applied to the outputs and VCC = 0V.
V+
VCC
400kΩ
TXIN
GND < TXIN < VCC
300Ω
TOUT
V- < VTOUT < V+
V-
FIGURE 2. TRANSMITTER
Receivers
The receiver inputs accept up to ±30V while presenting the
required 3kΩ to 7kΩ input impedance even it the power is off
(VCC = 0V). The receivers have a typical input threshold of
1.3V which is within the ±3V limits, known as the transition
region, of the RS-232 specifications. The receiver output is
0V to VCC. The output will be low whenever the input is
greater than 2.4V and high whenever the input is floating or
driven between +0.8V and -30V. The receivers feature 0.5V
hysteresis to improve noise rejection. The receiver Enable
line EN, when set to logic “1”, (HIN236, 239, 240, and 241)
disables the receiver outputs, placing them in the high
impedance mode. The receiver outputs are also placed in
the high impedance state when in shutdown mode.
VCC
RXIN
-30V < RXIN < +30V 5kΩ
ROUT
GND < VROUT < VCC
GND
FIGURE 3. RECEIVER
TIN
OR
RIN
TOUT
OR
ROUT
tPHL
tPLH
VOL
VOL
Average Propagation Delay =
tPHL + tPLH
2
FIGURE 4. PROPAGATION DELAY DEFINITION
8-38
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