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HD74HCT244P Ver la hoja de datos (PDF) - Renesas Electronics

Número de piezacomponentes DescripciónFabricante
HD74HCT244P Octal Buffers/Line Drivers/Line Receivers (with inverted 3-state outputs) Renesas
Renesas Electronics Renesas
HD74HCT244P Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
HD74HCT244
Octal Buffers/Line Drivers/Line Receivers
(with inverted 3-state outputs)
REJ03D0664–0200
(Previous ADE-205-553)
Rev.2.00
Mar 30, 2006
Description
The HD74HCT244 is a non-inverting buffer and has two active low enable (1G and 2G). Each enable independently
controls 4 buffers.
This device does not have schmitt trigger inputs.
Features
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: tpd (A to Y) = 10 ns typ (CL = 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: VCC = 4.5 to 5.5 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HCT244P
DILP-20 pin
PRDP0020AC-B
(DP-20NEV)
P
HD74HCT244FPEL SOP-20 pin (JEITA) PRSP0020DD-B
FP
(FP-20DAV)
HD74HCT244RPEL
SOP-20 pin (JEDEC)
PRSP0020DC-A
(FP-20DBV)
RP
HD74HCT244TELL TSSOP-20 pin
PTSP0020JB-A
(TTP-20DAV)
T
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
G
A
H
X
L
H
L
L
H : high level
L : low level
X : irrelevant
Z : off (high-impedance) state of a 3-state output
Output
Y
Z
H
L
Rev.2.00 Mar 30, 2006 page 1 of 6
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