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HD4043312 View Datasheet(PDF) - Renesas Electronics

Part NameDescriptionManufacturer
HD4043312 4-bit HMCS400-Series microcomputer with large-capacity memory Renesas
Renesas Electronics Renesas
HD4043312 Datasheet PDF : 80 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
HD404339 Series
IE
IM
LSON
SEM/SEMD
Allowed
REM/REMD
Allowed
TM/TMD
Allowed
IAOF
IF
ICSF
Not executed
Allowed
Allowed
ICEF
RAME
RSP
WDON
ADSF
DTON
Not executed
Allowed
Allowed
Not executed
Allowed
Inhibited
Not executed in active mode Allowed
Inhibited
Inhibited
Allowed
Allowed
Not used
Used in subactive mode
Not executed
Not executed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instruction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode. If the TM or TMD instruction is executed for
the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
Memory registers
$040 MR(0)
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)
$3C0
$3FF
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
PC13–PC0 : Program counter
ST: Status flag
CA: Carry flag
Bit 3
$3FC ST
$3FD PC10
$3FE CA
$3FF PC3
Bit 2
PC13
PC9
PC6
PC2
Bit 1
PC12
PC8
PC5
PC1
Bit 0
PC11
PC7
PC4
PC0
Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position
12
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