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HCPL-0314-560E View Datasheet(PDF) - Avago Technologies

Part Name
Description
Manufacturer
HCPL-0314-560E
AVAGO
Avago Technologies AVAGO
HCPL-0314-560E Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified.
Parameter
Propagation Delay Time to
High Output Level
Propagation Delay Time to
Low Output Level
Propagation Delay
Difference Between Any
Two Parts or Channels
Rise Time
Fall Time
Output High Level Common
Mode Transient Immunity
Output Low Level Common
Mode Transient Immunity
Symbol Min. Typ.
tPLH
0.1
0.2
tPHL
0.1
0.3
PDD
-0.5
tR
50
tF
50
|CMH| 25
35
|CML|
25
35
Max.
0.7
0.7
0.5
Test
Units Conditions Fig.
Note
µs
Rg = 47 , 10,11, 14
Cg = 3 nF, 12,13,
µs
f = 10 kHz, 14,17
Duty Cycle =
µs
50%,
IF = 8 mA,
10
VCC = 30 V
ns
ns
kV/µs TA = 25°C, 18
11
VCM = 1 kV
kV/µs
18
12
Package Characteristics
Parameter
Test
Symbol Min. Typ. Max. Units Conditions Fig. Note
Input-Output Momentary
VISO
3750
Withstand Voltage
Vrms TA=25°C,
8,9
RH<50% for
Input-Output Resistance
RI-O
1012
VI-O=500 V
9
Input-Output Capacitance CI-O
0.6
pF
Freq=1 MHz
Notes:
1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 0.4 A. See Application section for additional details on limiting IOL peak.
3. Derate linearly above 85°C, free air temperature at the rate of 4.0 mW/°C.
4. Input power dissipation does not require derating.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection
current limit II-O 5 µA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN
60747-5-2 Insulation Characteristics Table, if applicable.
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. PDD is the difference between tPHL and tPLH between any two parts or channels under the same test conditions.
11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse VCM to assure that the output
will remain in the high state (i.e. Vo > 6.0 V).
12. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e. Vo < 1.0 V).
13. This load condition approximates the gate load of a 1200 V/25 A IGBT.
14. The power supply current increases when operating frequency and Qg of the driven IGBT increases.
7
 

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