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HCF40163BC1 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
HCF40163BC1
ST-Microelectronics
STMicroelectronics ST-Microelectronics
HCF40163BC1 Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
HCC/HCF40160B-40161B-40162-40163
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 oC, CL = 50 pF, RL = 200 K,
typical temperature coefficent for all VDD values is 03 %/oC, all input rise and fall times= 20 ns)
Symbol
Parameter
tPLH Propagation Delay Time
tPHL Clock to Q
Test Conditions
Value
Unit
VDD (V) Min. Typ. Max.
5
200 400
10
80 160
ns
15
60 120
tPLH Propagation Delay Time
tPHL Clock to COUT
5
225 450
10
95 190
ns
tPLH Propagation Delay Time
tPHL
TE to COUT
15
70 140
5
125 250
10
55 110
ns
15
40 80
tsetup
Setup Time
Data to Clock
5
240 120
10
90
45
ns
15
60
30
tsetup
Setup Time
Load to Clock
5
240 120
10
90
45
ns
15
60
30
tsetup
Setup Time
PE or TE to Clock
5
340 170
10 140 70
ns
15 100 50
thold Hold Time
5
0
10
0
ns
15
0
tTHL Transition Time
tTLH
5
100 200
10
50 100
ns
15
40 80
tW CLock Input Pulse Width
5
170 85
10
70
35
ns
15
50
25
fCL Maximum Clock Input Frequency
5
2
3
10
5.5 8.5
MHz
15
8
12
tr tf Clock Input Rise or Fall Time *
200
70
ns
15
tPHL Propagation Delay Time (40160B, 40161B)
Clear to Q
5
250 500
10
110 220
ns
15
80 160
tsetup
Setup Time (40162B, 40163B)
Clear to Clock
5
340 170
10 140 70
ns
15 100 50
thold Hold Time (40162B, 40163B)
Clear to Clock
5
0
10
0
ns
15
0
trem Clear Removal Time (40162B, 40163B)
5
200 100
10 100 50
ns
15
70
35
tW Clear Input Pulse Width Low Level (40160B,
40161B)
5
170 85
10
70
35
ns
15
50
25
* If more than one unit is cascated in the parallel clocked application, tr should be made less than or equal to the sum of the fixed propagation delay
at 50 pF and the transition time of the carry output driving stage for the estimated capacitance
6/15
 

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