6006B3 View Datasheet(PDF) - EM Microelectronic - MARIN SA

Part Name

Description

Manufacturer

6006B3

Failsafe Watchdog

EM Microelectronic - MARIN SA 

R

Monitoring of the unregulated voltage require versions B1,

A2 and B2. The versions are based on the principle that VDD

rises with VIN on power-up and VDD holds up for a certain

time after VIN starts dropping on power-down. The version B1

has a 100 kΩ nominal resistance from VIN to VSS (internal

voltage divider). The versions A2, B2, A3 and B3 have high

impedance VIN inputs (see Fig. 7 and Table 4) for external

threshold voltage programming by a voltage divider on pin

VIN. The levels obtained are proportional to the internal levels

VSH, VSL and VRL on the chip itself (see Electrical

Specifications).

Timer Programming

With pin RC unconnected, the on-chip RC oscillator together

with its divider chain give a timeout TTO of typically 10 ms.

For programming a different TTO, an approximation for

calculating component values is given by the formula:

⎡

⎤

TTO

⎢

=⎢0.75

⎢

⎢⎣

+

(32 + C1) •1.6

5.5

+

VDD − 0.8

R1

⎥

⎥

⎥

⎥⎦

• 1.024

R1 min. = 10 kΩ, C1 max. = 1 µF

If R1 is in MΩ and C1 in pF, TTO will be in ms.

Thus, a resistor decreases and a capacitor increases the

interval to timeout. By using both external components,

excellent temperature stability of TTO can be achieved. With

TCL tied to either VDD or VSS, a precise square wave of

period 2 x TTO is generated at the output TO . The oscillator

and watchdog timer run so long as the chip is powered with

at least the minimum positive supply voltage specified (VON),

and so long as VIN remains above the level VRL after a

power-up sequence. If the timer function is not required,

input TCL should be tied to output TO to give a simple

voltage monitor (see Fig. 14).

H6006

Timer Clearing and RES Action

A negative edge or a negative pulse at the TCL input

longer than 150 ns will reset the timer and set TO high. If

a further TCL signal edge or pulse is applied before TTO

timeout, TO will stay high and the timer will again be reset

to zero (see Fig. 5). If no TCL signal is applied before the

TTO timeout, TO will start to generate a square wave of

period 2 x TTO starting with a low state. If no TCL signal is

applied during the first low state of TO , then the RES

output will go low and stay low until the next TCL signal,

or until a fresh power-up sequence.

Combined Voltage and Timer Action

The combination of voltage and timer action is illustrated by

the sequence of events shown in Fig. 6. One timeout period

after VIN reached VSH, during power-up, RES goes inactive

high. No TCL pulse will have any effect until this power-on

reset delay is completed. After completing the power-up

sequence the watchdog timer starts acting. If no TCL pulse

occurs, the timeout warning TO goes active low after one

timeout period TTO. After each subsequent timeout period

without a timer clear pulse TCL , TO changes its polarity

providing a square wave signal. RES activates at the end

of the first low state of the TO signal. A TCL pulse clears

the watchdog timer and resets the TO and RES output

inactive high again. A voltage drop below the VRL level

overrides the timer and immediately forces RES and

SAVE active low and disables TO . Any further TCL pulse

has no effect until the next power-up sequence has

complete

Typical Applications

Monitored

Voltage

R1 = 470 kΩ

Adress

Decoder SEL

Latched

Address Bus

C1 =

220 pF

RD

Microprocessor

RESET

IR 1

IR 2

TTO =~ 30 ms

>9 V Voltage

Regulator

VIN

TCL

RC

VSS

VDD

TO

SAVE

RES

5V

RAM

CS Disable

Fig. 11

Copyright © 2004, EM Microelectronic-Marin SA

6

www.emmicroelectronic.com

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