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AD261AND-3 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD261AND-3
ADI
Analog Devices ADI
AD261AND-3 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
AD261 CONFIGURATIONS
AD261
AD261-4
LATCH
F0
STTHARTEEE-
LINE 0
D
E
S0
LATCH
F1
D
E
LINE 1
THSRTAETEE-
2 S1
LATCH
F2
D
E
LINE 2
THSRTAETEE-
3 S2
LATCH
F3
D
E
LINE 3
THSRTAETEE-
4 S3
LATCH
F4
D
E
LINE 4
THSRTAETEE-
5 S4
ENABLEFLD 17
+5V dcFLD 16 +5V dc
5V dc RTN
5V RTNFLD 15
6 ENABLESYS
+5V dc
7 +5V dcSYS
5V dc RTN
8 5V RTNSYS
FIELD
SYSTEM
AD261-5
LATCH
F0
D
E
LINE 0
THSRTAETEE-
S0
LATCH
F1
D
E
LINE 1
THSRTAETEE-
2 S1
LATCH
F2
D
E
LINE 2
THSRTAETEE-
3 S2
LATCH
F3
D
E
LINE 3
THSRTAETEE-
4 S3
LATCH
F4
D
E
LINE 4
THSRTAETEE-
5 S4
ENABLEFLD 17
+5V dcFLD 16 +5V dc
5V dc RTN
5V RTNFLD 15
FIELD
6 ENABLESYS
+5V dc
7 +5V dcSYS
5V dc RTN
8 5V RTNSYS
SYSTEM
(Continued from page 1)
Field and System Enable Functions: Both the isolated and
nonisolated sides of the AD261 have ENABLE pins that three-
state all outputs. Upon reenabling these pins, all outputs are
updated to reflect the current input logic level.
CE Certifiable: Simply by adding the external bypass capacitors
at the supply pins, the AD261 can attain CE certification in
most applications (to the EMC directive) and conformance to
the low voltage (safety) directive is assured by the EN60950
certification.
Table I. Model Number and Pinout Function
Pin AD261-0 AD261-1 AD261-2 AD261-3 AD261-4 AD261-5
1 S0 (Xmt)
2 S1 (Xmt)
3 S2 (Xmt)
4 S3 (Xmt)
5 S4 (Xmt)
6 ENABLESYS
7
+5 V dcSYS
8
5 V RTNSYS
9–14
15 5 V RTNFLD
16 +5 V dcFLD
17 ENABLEFLD
18 F0 (Rcv)
19 F1 (Rcv)
20 F2 (Rcv)
21 F3 (Rcv)
22 F4 (Rcv)
S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Rcv)
S1 (Xmt) S1 (Xmt) S1 (Xmt) S1 (Rcv) S1 (Rcv)
S2 (Xmt) S2 (Xmt) S2 (Rcv) S2 (Rcv) S2 (Rcv)
S3 (Xmt) S3 (Rcv) S3 (Rcv) S3 (Rcv) S3 (Rcv)
S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Not Present
*
*
*
*
*
*
*
*
*
*
*
*
*
*
F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Xmt)
F1 (Rcv) F1 (Rcv) F1 (Rcv) F1 (Xmt) F1 (Xmt)
F2 (Rcv) F2 (Rcv) F2 (Xmt) F2 (Xmt) F2 (Xmt)
F3 (Rcv) F3 (Xmt) F3 (Xmt) F3 (Xmt) F3 (Xmt)
F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt)
*Pin function is the same on all models, as shown in the AD261-0 column.
GENERAL ATTRIBUTES
The AD261 provides five HCMOS compatible isolated logic
lines with 10 kV/µs common-mode transient immunity.
The case design and pin arrangement provides greater than
18 mm spacing between field and system side conductors, pro-
viding CSA/IS and IEC creepage spacing consistent with 750 V
mains isolation.
The five unidirectional logic lines have six possible combina-
tions of “ins” and “outs,” or transmitter/receiver pairs; hence
there are six AD261 part configurations (see Table I).
Each 20 MHz logic line has a Schmidt trigger input and a three-
state output (on the other side of the isolation barrier) and 14 ns of
propagation delay. A single enable pin on either side of the
barrier causes all outputs on that side to go three-state and all
inputs (driven pins) to ignore their inputs and retain their last
known state.
Note: All unused logic inputs (1–5) should be tied either high or low,
but not left floating.
Edge “fidelity,” or the difference in propagation time for rising
and falling edges, is typically less than ± 1 ns.
Power consumption, unlike opto-isolators, is a function of operat-
ing frequency. Each logic line barrier driver requires about 160 µA
per MHz and each receiver 40 µA per MHz plus, of course, 4 mA
total idle current (each side). The supply current diminishes
slightly with increasing temperature (about –0.03%/°C).
The total capacitance spanning the isolation barrier is less than
10 pF.
The minimum period of a pulse that can be accurately coupled
across the barrier is about 25 ns. Therefore the maximum
square-wave frequency of operation is 20 MHz.
REV. 0
–5–
 

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