GS9023A View Datasheet(PDF) - Gennum -> Semtech
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GS9023A Datasheet PDF : 37 Pages
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2.2.4 Audio Clock Input
The user must input a master audio clock (128 fs:
6.144MHz) at the ACLK clock terminal. This clock must be
synchronized with the video signal input to the GS9023A.
The audio word clock inputs WCINA and WCINB must be
grounded.
NOTE: The long term jitter present on the ACLK must be
less than half the audio clock period.
2.2.5 Audio Data Output
The serial audio data for channels 1 and 2 are output at the
AOUTA pin. The serial audio data for channels 3 and 4 are
output at the AOUTB pin. Both outputs are synchronized to
the rising edge of ACLK.
The GS9023A can demultiplex 20 or 24 bit audio data
samples. When 24 bit audio samples are detected, the
AUXEN pin and bit “A4ON” of Host Interface Register #1h
are set HIGH. When 20 bit audio samples are detected the
AUXEN pin and “A4ON” register bit are set LOW. When
AUXEN and “A4ON” are LOW, bits 4-7 of the AES/EBU
output data format are set to “0”. In the non-AES/EBU
formats, bits 0-3 are set to “0”. See Figure 14.
The GS9023A offers five predefined audio data output
formats, selected via the AM[2:0] pins, which are listed in
Table 12 and illustrated in Figure 14. The first four
predefined formats relate to non-AES/EBU audio data while
the fifth format corresponds to the AES/EBU audio format.
During reset, the audio outputs are forced LOW.
The GS9023A supports muting of the audio data outputs.
The output serial audio samples are forced to zero when the
MUTE pin or “MUTE” bit of Host Interface Register #4h are
set HIGH. The audio data outputs are also muted when
there is no video input signal.
TABLE 12 AUDIO OUTPUT FORMATS
FORMATS
WCOUT AM[2]
AOUT-MODE 0
Active
0
48kHz
AOUT-MODE 1
Active
0
48kHz
AOUT-MODE 2
Active
0
48kHz
AOUT-MODE 3
Active
0
48kHz
AOUT-AES/EBU
-
1
Not Used
-
1
Not Used
-
1
Not Used
-
1
AM[1]
0
0
1
1
0
0
1
1
AM[0]
0
1
0
1
0
1
0
1
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