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ADM1485JRZ View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADM1485JRZ
ADI
Analog Devices ADI
ADM1485JRZ Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADM1485–SPECIFICATIONS (VCC = 5 V ؎ 5%. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
DRIVER
Differential Output Voltage, VOD
VOD3
Δ|VOD| for Complementary Output States
Common-Mode Output Voltage VOC
Δ|VOD| for Complementary Output States
Output Short-Circuit Current (VOUT = High)
Output Short-Circuit Current (VOUT = Low)
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH
Logic Input Current (DE, DI)
RECEIVER
Differential Input Threshold Voltage, VTH
Input Voltage Hysteresis, ΔVTH
Input Resistance
Input Current (A, B)
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL
CMOS Output Voltage High, VOH
Short-Circuit Output Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
ICC (Outputs Enabled)
ICC (Outputs Disabled)
Specifications subject to change without notice.
Min Typ Max
5.0
2.0
5.0
1.5
5.0
1.5
5.0
0.2
3
0.2
35
250
35
250
0.8
2.0
± 1.0
–0.2
+0.2
70
12
1
–0.8
0.8
2.0
±1
0.4
4.0
7
85
± 1.0
1.0 2.2
0.6 1
Unit Test Conditions/Comments
V R = , Test Circuit 1
V VCC = 5 V, R = 50 Ω (RS-422), Test Circuit 1
V R = 27 Ω (RS-485), Test Circuit 1
V VTST = –7 V to +12 V, Test Circuit 2
V R = 27 Ω or 50 Ω, Test Circuit 1
V R = 27 Ω or 50 Ω, Test Circuit 1
V R = 27 Ω or 50 Ω
mA –7 V VO +12 V
mA –7 V VO +12 V
V
V
μA
V –7 V VCM +12 V
mV VCM = 0 V
kΩ –7 V VCM +12 V
mA VIN = +12 V
mA VIN = –7 V
V
V
μA
V IOUT = +4.0 mA
V IOUT = –4.0 mA
mA VOUT = GND or VCC
μA 0.4 V VOUT 2.4 V
mA Digital Inputs = GND or VCC
mA Digital Inputs = GND or VCC
TIMING SPECIFICATIONS (VCC = 5 V ؎ 5%. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Min Typ Max Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output tPLH, tPHL 2
Driver O/P to O/P tSKEW
Driver Rise/Fall Time tR, tF
Driver Enable to Output Valid
Driver Disable Timing
Matched Enable Switching
|tAZH –tBZL|, |tBZH –tAZL|
Matched Disable Switching
|tAHZ –tBLZ|, |tBHZ –tALZ|
RECEIVER
Propagation Delay Input to Output tPLH, tPHL 8
Skew |tPLH –tPHL|
Receiver Enable tEN1
Receiver Disable tEN2
Tx Pulse Width Distortion
Rx Pulse Width Distortion
10 15
15
8 15
10 25
10 25
02
02
15 30
5
5 20
5 20
1
1
ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3
ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3
ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3
ns RL = 110 Ω, CL = 50 pF, Test Circuit 4
ns RL = 110 Ω, CL = 50 pF, Test Circuit 4
ns RL = 110 Ω, CL = 50 pF, Test Circuit 4*
ns RL = 110 Ω, CL = 50 pF, Test Circuit 4*
ns CL = 15 pF, Test Circuit 5
ns CL = 15 pF, Test Circuit 5
ns CL = 15 pF, RL = 1 kΩ, Test Circuit 6
ns CL = 15 pF, RL = 1 kΩ, Test Circuit 6
ns
ns
*Guaranteed by characterization.
Specifications subject to change without notice.
–2–
REV. '
 

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