GS1540-CQR View Datasheet(PDF) - Gennum -> Semtech
Part Name
Description
Manufacturer
GS1540-CQR Datasheet PDF : 17 Pages
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PCLK_VCC
100
PCLK
27k
PCLK_VEE
Fig. 13 PCLK Output Circuit
DETAILED DESCRIPTION
The GS1540 is a single standard receiver for serial digital
HDTV signals at 1.485Gb/s and 1.485/1.001Gb/s.
UNIQUE SLEW PHASE LOCK LOOP (S-PLL):
A unique feature of the GS1540 is the innovative slew phase
lock loop (S-PLL). When a step phase change is applied to
the PLL, the output phase gains constant rate of change
with respect to time. This behaviour is termed slew.
Figure 16 shows an example of input and output phase
variation over time for slew and linear (conventional) PLLs.
Since the slewing is a nonlinear behavior, the small signal
analysis cannot be done in the same way as the standard
PLL. However, it is still possible to plot input jitter transfer
characteristics at a constant input jitter modulation.
DDO_EN
DDO_VCC
20k
2k
DDO_VEE
Fig. 14 DDO_EN Circuit
0.2
INPUT
0.1
OUTPUT
0.0
SLEW PLL RESPONSE
0.2
INPUT
0.1
OUTPUT
0.0
LINEAR (CONVENTIONAL) PLL RESPONSE
Fig. 16 PLL Characteristics
50
DDO
zDDO_VCC
Slew PLLs offer several advantages such as excellent noise
immunity. Because of the infinite bandwidth for an infinitely
small input jitter modulation (or jitter introduced by VCO),
the loop corrects for that immediately thus the small signal
noise of the VCO is cancelled. The GS1540 uses a very
50
clean, external VCO called the GO1515 (refer to the
GO1515 Data Sheet for details). In addition, the bi-level
DDO
digital phase detector provides constant loop bandwidth
that is predominantly independent of the data transition
density. The loop bandwidth of a conventional tri-stable
charge pump drops with reducing data transitions. During
pathological signals, the data transition density reduces
from 0.5 to 0.05, but the slew PLL’s performance essentially
remains unchanged.
DDO_VEE
Fig. 15 Serial (DDO) Output Stage Circuit
GENNUM CORPORATION
11 of 17
522 - 27 - 03
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