GM82C765 View Datasheet(PDF) - Hynix Semiconductor
Part Name
Description
Manufacturer
GM82C765 Datasheet PDF : 36 Pages
| |||
GM82C765B
* CLOCK GENERATION
This logical block provides all the clocks needed by
the GM82C765B. They are: Sampling clock (SCLK),
Write clock (WCLK), and the MASTER CLOCK
(MCLK). SCLK drives the DPLL Data Separator used
during data recovery. This Clocks’s frequency is
always 32 times the selected data rate. WCLK is used
by the encoder logic to place MFM or FM on the serial
WD-stream to the disk. WCLK always has a frequency
two times the selected data rate. MCLK is used by the
microsequencer. MCLK and MCLK clock all latches
in a two-phase scheme.
One microinstruction cycle is four MCLK cycles.
MCLK has a frequency times the FM data rate.
Table 9 presents the Clock Data Rate. Figure 6
illustrates the XTAL oscillator circuits for the 44-pin
PLCC configuration.
TABLE 9. CLOCK DATA RATE
DATA RATE
500Kbit/S
250Kbit/S
250Kbit/S
125Kbit/S
300Kbit/S
CODE
MFM
FM
MFM
FM
MFM
SLCK
16.0MHz
8.0MHz
8.0MHz
4.0MHz
9.6MHz
MCLK
4.0MHz
4.0MHz
2.0MHz
2.0MHz
2.4MHz
WCLK
1.0MHz
500.0MHz
500.0MHz
250.0MHz
600.0MHz
26
XT1
25
XT1
23
XT2
XT2 22
SERIES RESONANT
C4
XT2
9.6MHz
+ 100 ppm
R Series
= 30 ohm Max
C3
C Shunt
= 10 pf Max
C1
= 68 pf 5% mica
C2
= 56 pf 5% mica
C2
SERIES
RESONANT
9.6MHz
+ 100 ppm
C1
R Series
= 30 ohm Max
C Shunt
= 10 pf Max
C3
= 47 pf 5% mica
C4
= 15 pf 5% mica
Fig 6. XTAL Oscillator circuits for the 44 pin PLCC
21
|
|
Share Link: 